LCOV - code coverage report

Current view: top level - dev/pci/drm/radeon - si_dpm.c (source / functions) Hit Total Coverage Test: 6.4 Lines: 0 3161 0.0 % Date: 2018-10-19 03:25:38 Functions: 0 163 0.0 % Legend: Lines: hit not hit

Function Name	Hit count
si_apply_state_adjust_rules	0
si_calculate_adjusted_tdp_limits	0
si_calculate_cac_wintime	0
si_calculate_leakage_for_v	0
si_calculate_leakage_for_v_and_t	0
si_calculate_leakage_for_v_and_t_formula	0
si_calculate_leakage_for_v_formula	0
si_calculate_memory_refresh_rate	0
si_calculate_power_efficiency_ratio	0
si_calculate_sclk_params	0
si_check_s0_mc_reg_index	0
si_clear_vc	0
si_construct_voltage_tables	0
si_convert_mc_reg_table_entry_to_smc	0
si_convert_mc_reg_table_to_smc	0
si_convert_mc_registers	0
si_convert_power_level_to_smc	0
si_convert_power_state_to_smc	0
si_copy_vbios_mc_reg_table	0
si_disable_ulv	0
si_do_program_memory_timing_parameters	0
si_dpm_debugfs_print_current_performance_level	0
si_dpm_disable	0
si_dpm_display_configuration_changed	0
si_dpm_enable	0
si_dpm_fini	0
si_dpm_force_performance_level	0
si_dpm_get_current_mclk	0
si_dpm_get_current_sclk	0
si_dpm_init	0
si_dpm_late_enable	0
si_dpm_post_set_power_state	0
si_dpm_pre_set_power_state	0
si_dpm_set_power_state	0
si_dpm_setup_asic	0
si_dpm_start_smc	0
si_dpm_stop_smc	0
si_enable_acpi_power_management	0
si_enable_auto_throttle_source	0
si_enable_display_gap	0
si_enable_power_containment	0
si_enable_sclk_control	0
si_enable_smc_cac	0
si_enable_spread_spectrum	0
si_enable_thermal_protection	0
si_enable_voltage_control	0
si_fan_ctrl_get_fan_speed_percent	0
si_fan_ctrl_get_mode	0
si_fan_ctrl_set_default_mode	0
si_fan_ctrl_set_fan_speed_percent	0
si_fan_ctrl_set_mode	0
si_fan_ctrl_set_static_mode	0
si_fan_ctrl_start_smc_fan_control	0
si_fan_ctrl_stop_smc_fan_control	0
si_force_switch_to_arb_f0	0
si_get_cac_std_voltage_max_min	0
si_get_cac_std_voltage_step	0
si_get_current_pcie_speed	0
si_get_ddr3_mclk_frequency_ratio	0
si_get_leakage_vddc	0
si_get_leakage_voltage_from_leakage_index	0
si_get_lower_of_leakage_and_vce_voltage	0
si_get_maximum_link_speed	0
si_get_mclk_frequency_ratio	0
si_get_mvdd_configuration	0
si_get_pi	0
si_get_smc_power_scaling_factor	0
si_get_std_voltage_value	0
si_get_strobe_mode_settings	0
si_get_svi2_voltage_table	0
si_get_vce_clock_voltage	0
si_halt_smc	0
si_init_arb_table_index	0
si_init_dte_leakage_table	0
si_init_simplified_leakage_table	0
si_init_smc_spll_table	0
si_init_smc_table	0
si_initial_switch_from_arb_f0_to_f1	0
si_initialize_hardware_cac_manager	0
si_initialize_mc_reg_table	0
si_initialize_powertune_defaults	0
si_initialize_smc_cac_tables	0
si_initialize_smc_dte_tables	0
si_is_special_1gb_platform	0
si_is_state_ulv_compatible	0
si_notify_link_speed_change_after_state_change	0
si_notify_smc_display_change	0
si_parse_power_table	0
si_parse_pplib_clock_info	0
si_parse_pplib_non_clock_info	0
si_patch_dependency_tables_based_on_leakage	0
si_patch_single_dependency_table_based_on_leakage	0
si_populate_initial_mvdd_value	0
si_populate_mc_reg_addresses	0
si_populate_mc_reg_table	0
si_populate_mclk_value	0
si_populate_memory_timing_parameters	0
si_populate_mvdd_value	0
si_populate_phase_shedding_value	0
si_populate_power_containment_values	0
si_populate_sclk_value	0
si_populate_smc_acpi_state	0
si_populate_smc_initial_state	0
si_populate_smc_sp	0
si_populate_smc_t	0
si_populate_smc_tdp_limits	0
si_populate_smc_tdp_limits_2	0
si_populate_smc_voltage_table	0
si_populate_smc_voltage_tables	0
si_populate_sq_ramping_values	0
si_populate_std_voltage_value	0
si_populate_ulv_state	0
si_populate_voltage_value	0
si_power_control_set_level	0
si_process_firmware_header	0
si_program_cac_config_registers	0
si_program_display_gap	0
si_program_ds_registers	0
si_program_git	0
si_program_memory_timing_parameters	0
si_program_response_times	0
si_program_sstp	0
si_program_tp	0
si_program_tpp	0
si_program_ulv_memory_timing_parameters	0
si_program_vc	0
si_read_clock_registers	0
si_request_link_speed_change_before_state_change	0
si_reset_to_default	0
si_restrict_performance_levels_before_switch	0
si_resume_smc	0
si_scale_power_for_smc	0
si_send_msg_to_smc_with_parameter	0
si_set_dpm_event_sources	0
si_set_max_cu_value	0
si_set_mc_special_registers	0
si_set_pcie_lane_width_in_smc	0
si_set_power_state_conditionally_enable_ulv	0
si_set_s0_mc_reg_index	0
si_set_sw_state	0
si_set_temperature_range	0
si_set_valid_flag	0
si_set_vce_clock	0
si_setup_bsp	0
si_should_disable_uvd_powertune	0
si_start_dpm	0
si_stop_dpm	0
si_thermal_enable_alert	0
si_thermal_initialize	0
si_thermal_set_temperature_range	0
si_thermal_setup_fan_table	0
si_thermal_start_smc_fan_control	0
si_thermal_start_thermal_controller	0
si_thermal_stop_thermal_controller	0
si_trim_voltage_table_to_fit_state_table	0
si_update_dte_from_pl2	0
si_upload_firmware	0
si_upload_mc_reg_table	0
si_upload_smc_data	0
si_upload_sw_state	0
si_upload_ulv_state	0
si_validate_phase_shedding_tables	0
si_write_smc_soft_register	0

Generated by: LCOV version 1.13