Line data Source code
1 : /* $OpenBSD: if_iwmreg.h,v 1.28 2018/02/28 14:39:35 stsp Exp $ */
2 :
3 : /******************************************************************************
4 : *
5 : * This file is provided under a dual BSD/GPLv2 license. When using or
6 : * redistributing this file, you may do so under either license.
7 : *
8 : * GPL LICENSE SUMMARY
9 : *
10 : * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
11 : *
12 : * This program is free software; you can redistribute it and/or modify
13 : * it under the terms of version 2 of the GNU General Public License as
14 : * published by the Free Software Foundation.
15 : *
16 : * This program is distributed in the hope that it will be useful, but
17 : * WITHOUT ANY WARRANTY; without even the implied warranty of
18 : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 : * General Public License for more details.
20 : *
21 : * You should have received a copy of the GNU General Public License
22 : * along with this program; if not, write to the Free Software
23 : * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 : * USA
25 : *
26 : * The full GNU General Public License is included in this distribution
27 : * in the file called COPYING.
28 : *
29 : * Contact Information:
30 : * Intel Linux Wireless <ilw@linux.intel.com>
31 : * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 : *
33 : * BSD LICENSE
34 : *
35 : * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
36 : * All rights reserved.
37 : *
38 : * Redistribution and use in source and binary forms, with or without
39 : * modification, are permitted provided that the following conditions
40 : * are met:
41 : *
42 : * * Redistributions of source code must retain the above copyright
43 : * notice, this list of conditions and the following disclaimer.
44 : * * Redistributions in binary form must reproduce the above copyright
45 : * notice, this list of conditions and the following disclaimer in
46 : * the documentation and/or other materials provided with the
47 : * distribution.
48 : * * Neither the name Intel Corporation nor the names of its
49 : * contributors may be used to endorse or promote products derived
50 : * from this software without specific prior written permission.
51 : *
52 : * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 : * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 : * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 : * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 : * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 : * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 : * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 : * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 : * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 : * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 : * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 : *
64 : *****************************************************************************/
65 :
66 : /*
67 : * CSR (control and status registers)
68 : *
69 : * CSR registers are mapped directly into PCI bus space, and are accessible
70 : * whenever platform supplies power to device, even when device is in
71 : * low power states due to driver-invoked device resets
72 : * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
73 : *
74 : * Use iwl_write32() and iwl_read32() family to access these registers;
75 : * these provide simple PCI bus access, without waking up the MAC.
76 : * Do not use iwl_write_direct32() family for these registers;
77 : * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
78 : * The MAC (uCode processor, etc.) does not need to be powered up for accessing
79 : * the CSR registers.
80 : *
81 : * NOTE: Device does need to be awake in order to read this memory
82 : * via IWM_CSR_EEPROM and IWM_CSR_OTP registers
83 : */
84 : #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */
85 : #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
86 : #define IWM_CSR_INT (0x008) /* host interrupt status/ack */
87 : #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */
88 : #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/
89 : #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */
90 : #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/
91 : #define IWM_CSR_GP_CNTRL (0x024)
92 :
93 : /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */
94 : #define IWM_CSR_INT_PERIODIC_REG (0x005)
95 :
96 : /*
97 : * Hardware revision info
98 : * Bit fields:
99 : * 31-16: Reserved
100 : * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions
101 : * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
102 : * 1-0: "Dash" (-) value, as in A-1, etc.
103 : */
104 : #define IWM_CSR_HW_REV (0x028)
105 :
106 : /*
107 : * EEPROM and OTP (one-time-programmable) memory reads
108 : *
109 : * NOTE: Device must be awake, initialized via apm_ops.init(),
110 : * in order to read.
111 : */
112 : #define IWM_CSR_EEPROM_REG (0x02c)
113 : #define IWM_CSR_EEPROM_GP (0x030)
114 : #define IWM_CSR_OTP_GP_REG (0x034)
115 :
116 : #define IWM_CSR_GIO_REG (0x03C)
117 : #define IWM_CSR_GP_UCODE_REG (0x048)
118 : #define IWM_CSR_GP_DRIVER_REG (0x050)
119 :
120 : /*
121 : * UCODE-DRIVER GP (general purpose) mailbox registers.
122 : * SET/CLR registers set/clear bit(s) if "1" is written.
123 : */
124 : #define IWM_CSR_UCODE_DRV_GP1 (0x054)
125 : #define IWM_CSR_UCODE_DRV_GP1_SET (0x058)
126 : #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c)
127 : #define IWM_CSR_UCODE_DRV_GP2 (0x060)
128 :
129 : #define IWM_CSR_MBOX_SET_REG (0x088)
130 : #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20
131 :
132 : #define IWM_CSR_LED_REG (0x094)
133 : #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0)
134 : #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */
135 :
136 :
137 : /* GIO Chicken Bits (PCI Express bus link power management) */
138 : #define IWM_CSR_GIO_CHICKEN_BITS (0x100)
139 :
140 : /* Analog phase-lock-loop configuration */
141 : #define IWM_CSR_ANA_PLL_CFG (0x20c)
142 :
143 : /*
144 : * CSR Hardware Revision Workaround Register. Indicates hardware rev;
145 : * "step" determines CCK backoff for txpower calculation. Used for 4965 only.
146 : * See also IWM_CSR_HW_REV register.
147 : * Bit fields:
148 : * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
149 : * 1-0: "Dash" (-) value, as in C-1, etc.
150 : */
151 : #define IWM_CSR_HW_REV_WA_REG (0x22C)
152 :
153 : #define IWM_CSR_DBG_HPET_MEM_REG (0x240)
154 : #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250)
155 :
156 : /* Bits for IWM_CSR_HW_IF_CONFIG_REG */
157 : #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
158 : #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
159 : #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
160 : #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
161 : #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
162 : #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
163 : #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
164 : #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
165 :
166 : #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
167 : #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
168 : #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
169 : #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
170 : #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
171 : #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
172 :
173 : #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
174 : #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
175 : #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
176 : #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
177 : #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
178 : #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
179 : #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
180 :
181 : #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
182 : #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
183 :
184 : /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
185 : * acknowledged (reset) by host writing "1" to flagged bits. */
186 : #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
187 : #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
188 : #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
189 : #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
190 : #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
191 : #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
192 : #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
193 : #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
194 : #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
195 : #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
196 : #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
197 :
198 : #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \
199 : IWM_CSR_INT_BIT_HW_ERR | \
200 : IWM_CSR_INT_BIT_FH_TX | \
201 : IWM_CSR_INT_BIT_SW_ERR | \
202 : IWM_CSR_INT_BIT_RF_KILL | \
203 : IWM_CSR_INT_BIT_SW_RX | \
204 : IWM_CSR_INT_BIT_WAKEUP | \
205 : IWM_CSR_INT_BIT_ALIVE | \
206 : IWM_CSR_INT_BIT_RX_PERIODIC)
207 :
208 : /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
209 : #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
210 : #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
211 : #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
212 : #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
213 : #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
214 : #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
215 :
216 : #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \
217 : IWM_CSR_FH_INT_BIT_RX_CHNL1 | \
218 : IWM_CSR_FH_INT_BIT_RX_CHNL0)
219 :
220 : #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \
221 : IWM_CSR_FH_INT_BIT_TX_CHNL0)
222 :
223 : /* GPIO */
224 : #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
225 : #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
226 : #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
227 :
228 : /* RESET */
229 : #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
230 : #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
231 : #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
232 : #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
233 : #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
234 : #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
235 :
236 : /*
237 : * GP (general purpose) CONTROL REGISTER
238 : * Bit fields:
239 : * 27: HW_RF_KILL_SW
240 : * Indicates state of (platform's) hardware RF-Kill switch
241 : * 26-24: POWER_SAVE_TYPE
242 : * Indicates current power-saving mode:
243 : * 000 -- No power saving
244 : * 001 -- MAC power-down
245 : * 010 -- PHY (radio) power-down
246 : * 011 -- Error
247 : * 9-6: SYS_CONFIG
248 : * Indicates current system configuration, reflecting pins on chip
249 : * as forced high/low by device circuit board.
250 : * 4: GOING_TO_SLEEP
251 : * Indicates MAC is entering a power-saving sleep power-down.
252 : * Not a good time to access device-internal resources.
253 : * 3: MAC_ACCESS_REQ
254 : * Host sets this to request and maintain MAC wakeup, to allow host
255 : * access to device-internal resources. Host must wait for
256 : * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
257 : * device registers.
258 : * 2: INIT_DONE
259 : * Host sets this to put device into fully operational D0 power mode.
260 : * Host resets this after SW_RESET to put device into low power mode.
261 : * 0: MAC_CLOCK_READY
262 : * Indicates MAC (ucode processor, etc.) is powered up and can run.
263 : * Internal resources are accessible.
264 : * NOTE: This does not indicate that the processor is actually running.
265 : * NOTE: This does not indicate that device has completed
266 : * init or post-power-down restore of internal SRAM memory.
267 : * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
268 : * SRAM is restored and uCode is in normal operation mode.
269 : * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
270 : * do not need to save/restore it.
271 : * NOTE: After device reset, this bit remains "0" until host sets
272 : * INIT_DONE
273 : */
274 : #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
275 : #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
276 : #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
277 : #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
278 :
279 : #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
280 :
281 : #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
282 : #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
283 : #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
284 :
285 :
286 : /* HW REV */
287 : #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
288 : #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
289 :
290 : #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0)
291 : #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020)
292 : #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030)
293 : #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050)
294 : #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040)
295 : #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060)
296 : #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070)
297 : #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080)
298 : #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084)
299 : #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0)
300 : #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05
301 : #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05
302 : #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0)
303 : #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100)
304 : #define IWM_CSR_HW_REV_TYPE_105 (0x0000110)
305 : #define IWM_CSR_HW_REV_TYPE_135 (0x0000120)
306 : #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210)
307 : #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0)
308 :
309 : /* EEPROM REG */
310 : #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
311 : #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002)
312 : #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
313 : #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
314 :
315 : /* EEPROM GP */
316 : #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
317 : #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
318 : #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
319 : #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
320 : #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
321 : #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
322 :
323 : /* One-time-programmable memory general purpose reg */
324 : #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
325 : #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
326 : #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
327 : #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
328 :
329 : /* GP REG */
330 : #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
331 : #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000)
332 : #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
333 : #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
334 : #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
335 :
336 :
337 : /* CSR GIO */
338 : #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
339 :
340 : /*
341 : * UCODE-DRIVER GP (general purpose) mailbox register 1
342 : * Host driver and uCode write and/or read this register to communicate with
343 : * each other.
344 : * Bit fields:
345 : * 4: UCODE_DISABLE
346 : * Host sets this to request permanent halt of uCode, same as
347 : * sending CARD_STATE command with "halt" bit set.
348 : * 3: CT_KILL_EXIT
349 : * Host sets this to request exit from CT_KILL state, i.e. host thinks
350 : * device temperature is low enough to continue normal operation.
351 : * 2: CMD_BLOCKED
352 : * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
353 : * to release uCode to clear all Tx and command queues, enter
354 : * unassociated mode, and power down.
355 : * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
356 : * 1: SW_BIT_RFKILL
357 : * Host sets this when issuing CARD_STATE command to request
358 : * device sleep.
359 : * 0: MAC_SLEEP
360 : * uCode sets this when preparing a power-saving power-down.
361 : * uCode resets this when power-up is complete and SRAM is sane.
362 : * NOTE: device saves internal SRAM data to host when powering down,
363 : * and must restore this data after powering back up.
364 : * MAC_SLEEP is the best indication that restore is complete.
365 : * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
366 : * do not need to save/restore it.
367 : */
368 : #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
369 : #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002)
370 : #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
371 : #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
372 : #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
373 :
374 : /* GP Driver */
375 : #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
376 : #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
377 : #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
378 : #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
379 : #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
380 : #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
381 :
382 : #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
383 :
384 : /* GIO Chicken Bits (PCI Express bus link power management) */
385 : #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
386 : #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
387 :
388 : /* LED */
389 : #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
390 : #define IWM_CSR_LED_REG_TURN_ON (0x60)
391 : #define IWM_CSR_LED_REG_TURN_OFF (0x20)
392 :
393 : /* ANA_PLL */
394 : #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300)
395 :
396 : /* HPET MEM debug */
397 : #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
398 :
399 : /* DRAM INT TABLE */
400 : #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31)
401 : #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
402 : #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
403 :
404 : /* SECURE boot registers */
405 : #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100)
406 : #define IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP 0x00000001
407 : #define IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ 0x00000002
408 : #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100)
409 : #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100)
410 : #define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS 0x00000003
411 : #define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED 0x00000002
412 : #define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS 0x00000004
413 : #define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL 0x00000008
414 : #define IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL 0x00000010
415 :
416 : #define IWM_FH_UCODE_LOAD_STATUS 0x1af0
417 :
418 : #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000
419 :
420 : #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78
421 : #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c
422 :
423 : #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000
424 : #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400
425 :
426 : #define IWM_CSR_SECURE_TIME_OUT (100)
427 :
428 : /* extended range in FW SRAM */
429 : #define IWM_FW_MEM_EXTENDED_START 0x40000
430 : #define IWM_FW_MEM_EXTENDED_END 0x57FFF
431 :
432 : /* FW chicken bits */
433 : #define IWM_LMPM_CHICK 0xa01ff8
434 : #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01
435 :
436 : #define IWM_FH_TCSR_0_REG0 (0x1D00)
437 :
438 : /*
439 : * HBUS (Host-side Bus)
440 : *
441 : * HBUS registers are mapped directly into PCI bus space, but are used
442 : * to indirectly access device's internal memory or registers that
443 : * may be powered-down.
444 : *
445 : * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
446 : * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
447 : * to make sure the MAC (uCode processor, etc.) is powered up for accessing
448 : * internal resources.
449 : *
450 : * Do not use iwl_write32()/iwl_read32() family to access these registers;
451 : * these provide only simple PCI bus access, without waking up the MAC.
452 : */
453 : #define IWM_HBUS_BASE (0x400)
454 :
455 : /*
456 : * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
457 : * structures, error log, event log, verifying uCode load).
458 : * First write to address register, then read from or write to data register
459 : * to complete the job. Once the address register is set up, accesses to
460 : * data registers auto-increment the address by one dword.
461 : * Bit usage for address registers (read or write):
462 : * 0-31: memory address within device
463 : */
464 : #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c)
465 : #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010)
466 : #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018)
467 : #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c)
468 :
469 : /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
470 : #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030)
471 : #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
472 :
473 : /*
474 : * Registers for accessing device's internal peripheral registers
475 : * (e.g. SCD, BSM, etc.). First write to address register,
476 : * then read from or write to data register to complete the job.
477 : * Bit usage for address registers (read or write):
478 : * 0-15: register address (offset) within device
479 : * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
480 : */
481 : #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044)
482 : #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048)
483 : #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c)
484 : #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050)
485 :
486 : /* enable the ID buf for read */
487 : #define IWM_WFPM_PS_CTL_CLR 0xa0300c
488 : #define IWM_WFMP_MAC_ADDR_0 0xa03080
489 : #define IWM_WFMP_MAC_ADDR_1 0xa03084
490 : #define IWM_LMPM_PMG_EN 0xa01cec
491 : #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078
492 : #define IWM_RFIC_REG_RD 0xad0470
493 : #define IWM_WFPM_CTRL_REG 0xa03030
494 : #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000
495 : #define IWM_ENABLE_WFPM 0x80000000
496 :
497 : #define IWM_AUX_MISC_REG 0xa200b0
498 : #define IWM_HW_STEP_LOCATION_BITS 24
499 :
500 : #define IWM_AUX_MISC_MASTER1_EN 0xa20818
501 : #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1
502 : #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800
503 : #define IWM_RSA_ENABLE 0xa24b08
504 : #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0
505 : #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78
506 : #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000
507 : #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000
508 : #define IWM_SB_MODIFY_CFG_FLAG 0xa03088
509 : #define IWM_SB_CPU_1_STATUS 0xa01e30
510 : #define IWM_SB_CPU_2_STATUS 0Xa01e34
511 :
512 : /* Used to enable DBGM */
513 : #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c)
514 :
515 : /*
516 : * Per-Tx-queue write pointer (index, really!)
517 : * Indicates index to next TFD that driver will fill (1 past latest filled).
518 : * Bit usage:
519 : * 0-7: queue write index
520 : * 11-8: queue selector
521 : */
522 : #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060)
523 :
524 : /**********************************************************
525 : * CSR values
526 : **********************************************************/
527 : /*
528 : * host interrupt timeout value
529 : * used with setting interrupt coalescing timer
530 : * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
531 : *
532 : * default interrupt coalescing timer is 64 x 32 = 2048 usecs
533 : */
534 : #define IWM_HOST_INT_TIMEOUT_MAX (0xFF)
535 : #define IWM_HOST_INT_TIMEOUT_DEF (0x40)
536 : #define IWM_HOST_INT_TIMEOUT_MIN (0x0)
537 : #define IWM_HOST_INT_OPER_MODE (1 << 31)
538 :
539 : /*****************************************************************************
540 : * 7000/3000 series SHR DTS addresses *
541 : *****************************************************************************/
542 :
543 : /* Diode Results Register Structure: */
544 : #define IWM_DTS_DIODE_REG_DIG_VAL 0x000000FF /* bits [7:0] */
545 : #define IWM_DTS_DIODE_REG_VREF_LOW 0x0000FF00 /* bits [15:8] */
546 : #define IWM_DTS_DIODE_REG_VREF_HIGH 0x00FF0000 /* bits [23:16] */
547 : #define IWM_DTS_DIODE_REG_VREF_ID 0x03000000 /* bits [25:24] */
548 : #define IWM_DTS_DIODE_REG_PASS_ONCE 0x80000000 /* bits [31:31] */
549 : #define IWM_DTS_DIODE_REG_FLAGS_MSK 0xFF000000 /* bits [31:24] */
550 : /* Those are the masks INSIDE the flags bit-field: */
551 : #define IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS 0
552 : #define IWM_DTS_DIODE_REG_FLAGS_VREFS_ID 0x00000003 /* bits [1:0] */
553 : #define IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS 7
554 : #define IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE 0x00000080 /* bits [7:7] */
555 :
556 : /**
557 : * uCode API flags
558 : * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
559 : * was a separate TLV but moved here to save space.
560 : * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
561 : * treats good CRC threshold as a boolean
562 : * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
563 : * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
564 : * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS
565 : * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
566 : * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
567 : * offload profile config command.
568 : * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api
569 : * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API.
570 : * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
571 : * (rather than two) IPv6 addresses
572 : * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API
573 : * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
574 : * from the probe request template.
575 : * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping
576 : * connection when going back to D0
577 : * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
578 : * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
579 : * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan.
580 : * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API
581 : * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command
582 : * containing CAM (Continuous Active Mode) indication.
583 : * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a
584 : * single bound interface).
585 : * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD
586 : * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS.
587 : * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
588 : * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering.
589 : * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients
590 : *
591 : */
592 : #define IWM_UCODE_TLV_FLAGS_PAN (1 << 0)
593 : #define IWM_UCODE_TLV_FLAGS_NEWSCAN (1 << 1)
594 : #define IWM_UCODE_TLV_FLAGS_MFP (1 << 2)
595 : #define IWM_UCODE_TLV_FLAGS_P2P (1 << 3)
596 : #define IWM_UCODE_TLV_FLAGS_DW_BC_TABLE (1 << 4)
597 : #define IWM_UCODE_TLV_FLAGS_NEWBT_COEX (1 << 5)
598 : #define IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT (1 << 6)
599 : #define IWM_UCODE_TLV_FLAGS_SHORT_BL (1 << 7)
600 : #define IWM_UCODE_TLV_FLAGS_RX_ENERGY_API (1 << 8)
601 : #define IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 (1 << 9)
602 : #define IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS (1 << 10)
603 : #define IWM_UCODE_TLV_FLAGS_BF_UPDATED (1 << 11)
604 : #define IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID (1 << 12)
605 : #define IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API (1 << 14)
606 : #define IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL (1 << 15)
607 : #define IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE (1 << 16)
608 : #define IWM_UCODE_TLV_FLAGS_SCHED_SCAN (1 << 17)
609 : #define IWM_UCODE_TLV_FLAGS_STA_KEY_CMD (1 << 19)
610 : #define IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD (1 << 20)
611 : #define IWM_UCODE_TLV_FLAGS_P2P_PS (1 << 21)
612 : #define IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM (1 << 22)
613 : #define IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM (1 << 23)
614 : #define IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT (1 << 24)
615 : #define IWM_UCODE_TLV_FLAGS_EBS_SUPPORT (1 << 25)
616 : #define IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD (1 << 26)
617 : #define IWM_UCODE_TLV_FLAGS_BCAST_FILTERING (1 << 29)
618 : #define IWM_UCODE_TLV_FLAGS_GO_UAPSD (1 << 30)
619 : #define IWM_UCODE_TLV_FLAGS_LTE_COEX (1 << 31)
620 :
621 : #define IWM_UCODE_TLV_FLAG_BITS \
622 : "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERGY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFFL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX"
623 :
624 : /**
625 : * uCode TLV api
626 : * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time
627 : * longer than the passive one, which is essential for fragmented scan.
628 : * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source.
629 : * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header
630 : * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params
631 : * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority
632 : * instead of 3.
633 : * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size
634 : * (command version 3) that supports per-chain limits
635 : *
636 : * @IWM_NUM_UCODE_TLV_API: number of bits used
637 : */
638 : #define IWM_UCODE_TLV_API_FRAGMENTED_SCAN (1 << 8)
639 : #define IWM_UCODE_TLV_API_WIFI_MCC_UPDATE (1 << 9)
640 : #define IWM_UCODE_TLV_API_WIDE_CMD_HDR (1 << 14)
641 : #define IWM_UCODE_TLV_API_LQ_SS_PARAMS (1 << 18)
642 : #define IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY (1 << 24)
643 : #define IWM_UCODE_TLV_API_TX_POWER_CHAIN (1 << 27)
644 :
645 : #define IWM_NUM_UCODE_TLV_API = 32
646 :
647 : #define IWM_UCODE_TLV_API_BITS \
648 : "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN"
649 :
650 : /**
651 : * uCode capabilities
652 : * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3
653 : * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory
654 : * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan.
655 : * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer
656 : * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM)
657 : * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality
658 : * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current
659 : * tx power value into TPC Report action frame and Link Measurement Report
660 : * action frame
661 : * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current
662 : * channel in DS parameter set element in probe requests.
663 : * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in
664 : * probe requests.
665 : * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests
666 : * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA),
667 : * which also implies support for the scheduler configuration command
668 : * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching
669 : * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image
670 : * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command
671 : * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command
672 : * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command
673 : * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload
674 : * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics
675 : * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD
676 : * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running
677 : * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different
678 : * sources for the MCC. This TLV bit is a future replacement to
679 : * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR
680 : * is supported.
681 : * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC
682 : * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan
683 : * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN
684 : * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported,
685 : * 0=no support)
686 : * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement
687 : * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts
688 : * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT
689 : * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what
690 : * antenna the beacon should be transmitted
691 : * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon
692 : * from AP and will send it upon d0i3 exit.
693 : * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2
694 : * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill
695 : * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature
696 : * thresholds reporting
697 : * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command
698 : * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in
699 : * regular image.
700 : * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared
701 : * memory addresses from the firmware.
702 : * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement
703 : * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported,
704 : * 0=no support)
705 : *
706 : * @IWM_NUM_UCODE_TLV_CAPA: number of bits used
707 : */
708 : #define IWM_UCODE_TLV_CAPA_D0I3_SUPPORT 0
709 : #define IWM_UCODE_TLV_CAPA_LAR_SUPPORT 1
710 : #define IWM_UCODE_TLV_CAPA_UMAC_SCAN 2
711 : #define IWM_UCODE_TLV_CAPA_BEAMFORMER 3
712 : #define IWM_UCODE_TLV_CAPA_TOF_SUPPORT 5
713 : #define IWM_UCODE_TLV_CAPA_TDLS_SUPPORT 6
714 : #define IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT 8
715 : #define IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT 9
716 : #define IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT 10
717 : #define IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT 11
718 : #define IWM_UCODE_TLV_CAPA_DQA_SUPPORT 12
719 : #define IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH 13
720 : #define IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG 17
721 : #define IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT 18
722 : #define IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT 19
723 : #define IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT 20
724 : #define IWM_UCODE_TLV_CAPA_CSUM_SUPPORT 21
725 : #define IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS 22
726 : #define IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD 26
727 : #define IWM_UCODE_TLV_CAPA_BT_COEX_PLCR 28
728 : #define IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC 29
729 : #define IWM_UCODE_TLV_CAPA_BT_COEX_RRC 30
730 : #define IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT 31
731 : #define IWM_UCODE_TLV_CAPA_NAN_SUPPORT 34
732 : #define IWM_UCODE_TLV_CAPA_UMAC_UPLOAD 35
733 : #define IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE 64
734 : #define IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS 65
735 : #define IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT 67
736 : #define IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT 68
737 : #define IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION 71
738 : #define IWM_UCODE_TLV_CAPA_BEACON_STORING 72
739 : #define IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 73
740 : #define IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW 74
741 : #define IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT 75
742 : #define IWM_UCODE_TLV_CAPA_CTDP_SUPPORT 76
743 : #define IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED 77
744 : #define IWM_UCODE_TLV_CAPA_LMAC_UPLOAD 79
745 : #define IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 80
746 : #define IWM_UCODE_TLV_CAPA_LQM_SUPPORT 81
747 :
748 : #define IWM_NUM_UCODE_TLV_CAPA 128
749 :
750 : /* The default calibrate table size if not specified by firmware file */
751 : #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
752 : #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19
753 : #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253
754 :
755 : /* The default max probe length if not specified by the firmware file */
756 : #define IWM_DEFAULT_MAX_PROBE_LENGTH 200
757 :
758 : /*
759 : * For 16.0 uCode and above, there is no differentiation between sections,
760 : * just an offset to the HW address.
761 : */
762 : #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC
763 : #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB
764 :
765 : /* uCode version contains 4 values: Major/Minor/API/Serial */
766 : #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
767 : #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
768 : #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
769 : #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
770 :
771 : /*
772 : * Calibration control struct.
773 : * Sent as part of the phy configuration command.
774 : * @flow_trigger: bitmap for which calibrations to perform according to
775 : * flow triggers.
776 : * @event_trigger: bitmap for which calibrations to perform according to
777 : * event triggers.
778 : */
779 : struct iwm_tlv_calib_ctrl {
780 : uint32_t flow_trigger;
781 : uint32_t event_trigger;
782 : } __packed;
783 :
784 : #define IWM_FW_PHY_CFG_RADIO_TYPE_POS 0
785 : #define IWM_FW_PHY_CFG_RADIO_TYPE (0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS)
786 : #define IWM_FW_PHY_CFG_RADIO_STEP_POS 2
787 : #define IWM_FW_PHY_CFG_RADIO_STEP (0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS)
788 : #define IWM_FW_PHY_CFG_RADIO_DASH_POS 4
789 : #define IWM_FW_PHY_CFG_RADIO_DASH (0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS)
790 : #define IWM_FW_PHY_CFG_TX_CHAIN_POS 16
791 : #define IWM_FW_PHY_CFG_TX_CHAIN (0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS)
792 : #define IWM_FW_PHY_CFG_RX_CHAIN_POS 20
793 : #define IWM_FW_PHY_CFG_RX_CHAIN (0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS)
794 :
795 : #define IWM_UCODE_MAX_CS 1
796 :
797 : /**
798 : * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW.
799 : * @cipher: a cipher suite selector
800 : * @flags: cipher scheme flags (currently reserved for a future use)
801 : * @hdr_len: a size of MPDU security header
802 : * @pn_len: a size of PN
803 : * @pn_off: an offset of pn from the beginning of the security header
804 : * @key_idx_off: an offset of key index byte in the security header
805 : * @key_idx_mask: a bit mask of key_idx bits
806 : * @key_idx_shift: bit shift needed to get key_idx
807 : * @mic_len: mic length in bytes
808 : * @hw_cipher: a HW cipher index used in host commands
809 : */
810 : struct iwm_fw_cipher_scheme {
811 : uint32_t cipher;
812 : uint8_t flags;
813 : uint8_t hdr_len;
814 : uint8_t pn_len;
815 : uint8_t pn_off;
816 : uint8_t key_idx_off;
817 : uint8_t key_idx_mask;
818 : uint8_t key_idx_shift;
819 : uint8_t mic_len;
820 : uint8_t hw_cipher;
821 : } __packed;
822 :
823 : /**
824 : * struct iwm_fw_cscheme_list - a cipher scheme list
825 : * @size: a number of entries
826 : * @cs: cipher scheme entries
827 : */
828 : struct iwm_fw_cscheme_list {
829 : uint8_t size;
830 : struct iwm_fw_cipher_scheme cs[];
831 : } __packed;
832 :
833 : /* v1/v2 uCode file layout */
834 : struct iwm_ucode_header {
835 : uint32_t ver; /* major/minor/API/serial */
836 : union {
837 : struct {
838 : uint32_t inst_size; /* bytes of runtime code */
839 : uint32_t data_size; /* bytes of runtime data */
840 : uint32_t init_size; /* bytes of init code */
841 : uint32_t init_data_size; /* bytes of init data */
842 : uint32_t boot_size; /* bytes of bootstrap code */
843 : uint8_t data[0]; /* in same order as sizes */
844 : } v1;
845 : struct {
846 : uint32_t build; /* build number */
847 : uint32_t inst_size; /* bytes of runtime code */
848 : uint32_t data_size; /* bytes of runtime data */
849 : uint32_t init_size; /* bytes of init code */
850 : uint32_t init_data_size; /* bytes of init data */
851 : uint32_t boot_size; /* bytes of bootstrap code */
852 : uint8_t data[0]; /* in same order as sizes */
853 : } v2;
854 : } u;
855 : };
856 :
857 : /*
858 : * new TLV uCode file layout
859 : *
860 : * The new TLV file format contains TLVs, that each specify
861 : * some piece of data.
862 : */
863 :
864 : #define IWM_UCODE_TLV_INVALID 0 /* unused */
865 : #define IWM_UCODE_TLV_INST 1
866 : #define IWM_UCODE_TLV_DATA 2
867 : #define IWM_UCODE_TLV_INIT 3
868 : #define IWM_UCODE_TLV_INIT_DATA 4
869 : #define IWM_UCODE_TLV_BOOT 5
870 : #define IWM_UCODE_TLV_PROBE_MAX_LEN 6 /* a uint32_t value */
871 : #define IWM_UCODE_TLV_PAN 7
872 : #define IWM_UCODE_TLV_RUNT_EVTLOG_PTR 8
873 : #define IWM_UCODE_TLV_RUNT_EVTLOG_SIZE 9
874 : #define IWM_UCODE_TLV_RUNT_ERRLOG_PTR 10
875 : #define IWM_UCODE_TLV_INIT_EVTLOG_PTR 11
876 : #define IWM_UCODE_TLV_INIT_EVTLOG_SIZE 12
877 : #define IWM_UCODE_TLV_INIT_ERRLOG_PTR 13
878 : #define IWM_UCODE_TLV_ENHANCE_SENS_TBL 14
879 : #define IWM_UCODE_TLV_PHY_CALIBRATION_SIZE 15
880 : #define IWM_UCODE_TLV_WOWLAN_INST 16
881 : #define IWM_UCODE_TLV_WOWLAN_DATA 17
882 : #define IWM_UCODE_TLV_FLAGS 18
883 : #define IWM_UCODE_TLV_SEC_RT 19
884 : #define IWM_UCODE_TLV_SEC_INIT 20
885 : #define IWM_UCODE_TLV_SEC_WOWLAN 21
886 : #define IWM_UCODE_TLV_DEF_CALIB 22
887 : #define IWM_UCODE_TLV_PHY_SKU 23
888 : #define IWM_UCODE_TLV_SECURE_SEC_RT 24
889 : #define IWM_UCODE_TLV_SECURE_SEC_INIT 25
890 : #define IWM_UCODE_TLV_SECURE_SEC_WOWLAN 26
891 : #define IWM_UCODE_TLV_NUM_OF_CPU 27
892 : #define IWM_UCODE_TLV_CSCHEME 28
893 :
894 : /*
895 : * Following two are not in our base tag, but allow
896 : * handling ucode version 9.
897 : */
898 : #define IWM_UCODE_TLV_API_CHANGES_SET 29
899 : #define IWM_UCODE_TLV_ENABLED_CAPABILITIES 30
900 : #define IWM_UCODE_TLV_N_SCAN_CHANNELS 31
901 : #define IWM_UCODE_TLV_PAGING 32
902 : #define IWM_UCODE_TLV_SEC_RT_USNIFFER 34
903 : #define IWM_UCODE_TLV_SDIO_ADMA_ADDR 35
904 : #define IWM_UCODE_TLV_FW_VERSION 36
905 : #define IWM_UCODE_TLV_FW_DBG_DEST 38
906 : #define IWM_UCODE_TLV_FW_DBG_CONF 39
907 : #define IWM_UCODE_TLV_FW_DBG_TRIGGER 40
908 : #define IWM_UCODE_TLV_FW_GSCAN_CAPA 50
909 : #define IWM_UCODE_TLV_FW_MEM_SEG 51
910 :
911 : struct iwm_ucode_tlv {
912 : uint32_t type; /* see above */
913 : uint32_t length; /* not including type/length fields */
914 : uint8_t data[0];
915 : };
916 :
917 : struct iwm_ucode_api {
918 : uint32_t api_index;
919 : uint32_t api_flags;
920 : } __packed;
921 :
922 : struct iwm_ucode_capa {
923 : uint32_t api_index;
924 : uint32_t api_capa;
925 : } __packed;
926 :
927 : #define IWM_TLV_UCODE_MAGIC 0x0a4c5749
928 :
929 : struct iwm_tlv_ucode_header {
930 : /*
931 : * The TLV style ucode header is distinguished from
932 : * the v1/v2 style header by first four bytes being
933 : * zero, as such is an invalid combination of
934 : * major/minor/API/serial versions.
935 : */
936 : uint32_t zero;
937 : uint32_t magic;
938 : uint8_t human_readable[64];
939 : uint32_t ver; /* major/minor/API/serial */
940 : uint32_t build;
941 : uint64_t ignore;
942 : /*
943 : * The data contained herein has a TLV layout,
944 : * see above for the TLV header and types.
945 : * Note that each TLV is padded to a length
946 : * that is a multiple of 4 for alignment.
947 : */
948 : uint8_t data[0];
949 : };
950 :
951 : /*
952 : * Registers in this file are internal, not PCI bus memory mapped.
953 : * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers.
954 : */
955 : #define IWM_PRPH_BASE (0x00000)
956 : #define IWM_PRPH_END (0xFFFFF)
957 :
958 : /* APMG (power management) constants */
959 : #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000)
960 : #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000)
961 : #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004)
962 : #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008)
963 : #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c)
964 : #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010)
965 : #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014)
966 : #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c)
967 : #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020)
968 : #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058)
969 : #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C)
970 :
971 : #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
972 : #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
973 : #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
974 :
975 : #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
976 : #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
977 : #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
978 : #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
979 : #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
980 : #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
981 : #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
982 :
983 : #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
984 :
985 : #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000)
986 :
987 : /* Device system time */
988 : #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C
989 :
990 : /* Device NMI register */
991 : #define IWM_DEVICE_SET_NMI_REG 0x00a01c30
992 : #define IWM_DEVICE_SET_NMI_VAL_HW 0x01
993 : #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80
994 : #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24
995 : #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000
996 :
997 : /*
998 : * Device reset for family 8000
999 : * write to bit 24 in order to reset the CPU
1000 : */
1001 : #define IWM_RELEASE_CPU_RESET 0x300c
1002 : #define IWM_RELEASE_CPU_RESET_BIT 0x1000000
1003 :
1004 :
1005 : /*****************************************************************************
1006 : * 7000/3000 series SHR DTS addresses *
1007 : *****************************************************************************/
1008 :
1009 : #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024)
1010 : #define IWM_DTSC_CFG_MODE (0x00a10604)
1011 : #define IWM_DTSC_VREF_AVG (0x00a10648)
1012 : #define IWM_DTSC_VREF5_AVG (0x00a1064c)
1013 : #define IWM_DTSC_CFG_MODE_PERIODIC (0x2)
1014 : #define IWM_DTSC_PTAT_AVG (0x00a10650)
1015 :
1016 :
1017 : /**
1018 : * Tx Scheduler
1019 : *
1020 : * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
1021 : * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
1022 : * host DRAM. It steers each frame's Tx command (which contains the frame
1023 : * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
1024 : * device. A queue maps to only one (selectable by driver) Tx DMA channel,
1025 : * but one DMA channel may take input from several queues.
1026 : *
1027 : * Tx DMA FIFOs have dedicated purposes.
1028 : *
1029 : * For 5000 series and up, they are used differently
1030 : * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
1031 : *
1032 : * 0 -- EDCA BK (background) frames, lowest priority
1033 : * 1 -- EDCA BE (best effort) frames, normal priority
1034 : * 2 -- EDCA VI (video) frames, higher priority
1035 : * 3 -- EDCA VO (voice) and management frames, highest priority
1036 : * 4 -- unused
1037 : * 5 -- unused
1038 : * 6 -- unused
1039 : * 7 -- Commands
1040 : *
1041 : * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
1042 : * In addition, driver can map the remaining queues to Tx DMA/FIFO
1043 : * channels 0-3 to support 11n aggregation via EDCA DMA channels.
1044 : *
1045 : * The driver sets up each queue to work in one of two modes:
1046 : *
1047 : * 1) Scheduler-Ack, in which the scheduler automatically supports a
1048 : * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
1049 : * contains TFDs for a unique combination of Recipient Address (RA)
1050 : * and Traffic Identifier (TID), that is, traffic of a given
1051 : * Quality-Of-Service (QOS) priority, destined for a single station.
1052 : *
1053 : * In scheduler-ack mode, the scheduler keeps track of the Tx status of
1054 : * each frame within the BA window, including whether it's been transmitted,
1055 : * and whether it's been acknowledged by the receiving station. The device
1056 : * automatically processes block-acks received from the receiving STA,
1057 : * and reschedules un-acked frames to be retransmitted (successful
1058 : * Tx completion may end up being out-of-order).
1059 : *
1060 : * The driver must maintain the queue's Byte Count table in host DRAM
1061 : * for this mode.
1062 : * This mode does not support fragmentation.
1063 : *
1064 : * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
1065 : * The device may automatically retry Tx, but will retry only one frame
1066 : * at a time, until receiving ACK from receiving station, or reaching
1067 : * retry limit and giving up.
1068 : *
1069 : * The command queue (#4/#9) must use this mode!
1070 : * This mode does not require use of the Byte Count table in host DRAM.
1071 : *
1072 : * Driver controls scheduler operation via 3 means:
1073 : * 1) Scheduler registers
1074 : * 2) Shared scheduler data base in internal SRAM
1075 : * 3) Shared data in host DRAM
1076 : *
1077 : * Initialization:
1078 : *
1079 : * When loading, driver should allocate memory for:
1080 : * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
1081 : * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
1082 : * (1024 bytes for each queue).
1083 : *
1084 : * After receiving "Alive" response from uCode, driver must initialize
1085 : * the scheduler (especially for queue #4/#9, the command queue, otherwise
1086 : * the driver can't issue commands!):
1087 : */
1088 : #define IWM_SCD_MEM_LOWER_BOUND (0x0000)
1089 :
1090 : /**
1091 : * Max Tx window size is the max number of contiguous TFDs that the scheduler
1092 : * can keep track of at one time when creating block-ack chains of frames.
1093 : * Note that "64" matches the number of ack bits in a block-ack packet.
1094 : */
1095 : #define IWM_SCD_WIN_SIZE 64
1096 : #define IWM_SCD_FRAME_LIMIT 64
1097 :
1098 : #define IWM_SCD_TXFIFO_POS_TID (0)
1099 : #define IWM_SCD_TXFIFO_POS_RA (4)
1100 : #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
1101 :
1102 : /* agn SCD */
1103 : #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0)
1104 : #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
1105 : #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4)
1106 : #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
1107 : #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000)
1108 :
1109 : #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
1110 : #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
1111 : #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
1112 : #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
1113 : #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
1114 : #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
1115 : #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
1116 : #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
1117 : #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0)
1118 : #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18)
1119 :
1120 : /* Context Data */
1121 : #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600)
1122 : #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
1123 :
1124 : /* Tx status */
1125 : #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
1126 : #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
1127 :
1128 : /* Translation Data */
1129 : #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
1130 : #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808)
1131 :
1132 : #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\
1133 : (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
1134 :
1135 : #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\
1136 : (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))
1137 :
1138 : #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \
1139 : ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
1140 :
1141 : #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00)
1142 :
1143 : #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0)
1144 : #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8)
1145 : #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c)
1146 : #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10)
1147 : #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14)
1148 : #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8)
1149 : #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244)
1150 : #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248)
1151 : #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108)
1152 : #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8)
1153 : #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254)
1154 :
1155 : static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl)
1156 : {
1157 : if (chnl < 20)
1158 : return IWM_SCD_BASE + 0x18 + chnl * 4;
1159 : return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4;
1160 : }
1161 :
1162 0 : static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl)
1163 : {
1164 0 : if (chnl < 20)
1165 0 : return IWM_SCD_BASE + 0x68 + chnl * 4;
1166 0 : return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4;
1167 0 : }
1168 :
1169 0 : static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl)
1170 : {
1171 0 : if (chnl < 20)
1172 0 : return IWM_SCD_BASE + 0x10c + chnl * 4;
1173 0 : return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4;
1174 0 : }
1175 :
1176 : /*********************** END TX SCHEDULER *************************************/
1177 :
1178 : /* Oscillator clock */
1179 : #define IWM_OSC_CLK (0xa04068)
1180 : #define IWM_OSC_CLK_FORCE_CONTROL (0x8)
1181 :
1182 : /****************************/
1183 : /* Flow Handler Definitions */
1184 : /****************************/
1185 :
1186 : /**
1187 : * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
1188 : * Addresses are offsets from device's PCI hardware base address.
1189 : */
1190 : #define IWM_FH_MEM_LOWER_BOUND (0x1000)
1191 : #define IWM_FH_MEM_UPPER_BOUND (0x2000)
1192 :
1193 : /**
1194 : * Keep-Warm (KW) buffer base address.
1195 : *
1196 : * Driver must allocate a 4KByte buffer that is for keeping the
1197 : * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
1198 : * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
1199 : * from going into a power-savings mode that would cause higher DRAM latency,
1200 : * and possible data over/under-runs, before all Tx/Rx is complete.
1201 : *
1202 : * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
1203 : * of the buffer, which must be 4K aligned. Once this is set up, the device
1204 : * automatically invokes keep-warm accesses when normal accesses might not
1205 : * be sufficient to maintain fast DRAM response.
1206 : *
1207 : * Bit fields:
1208 : * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
1209 : */
1210 : #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C)
1211 :
1212 :
1213 : /**
1214 : * TFD Circular Buffers Base (CBBC) addresses
1215 : *
1216 : * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
1217 : * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
1218 : * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04
1219 : * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
1220 : * aligned (address bits 0-7 must be 0).
1221 : * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers
1222 : * for them are in different places.
1223 : *
1224 : * Bit fields in each pointer register:
1225 : * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
1226 : */
1227 : #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1228 : #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10)
1229 : #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0)
1230 : #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1231 : #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20)
1232 : #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80)
1233 :
1234 : /* Find TFD CB base pointer for given queue */
1235 0 : static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl)
1236 : {
1237 0 : if (chnl < 16)
1238 0 : return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl;
1239 0 : if (chnl < 20)
1240 0 : return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
1241 0 : return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
1242 0 : }
1243 :
1244 :
1245 : /**
1246 : * Rx SRAM Control and Status Registers (RSCSR)
1247 : *
1248 : * These registers provide handshake between driver and device for the Rx queue
1249 : * (this queue handles *all* command responses, notifications, Rx data, etc.
1250 : * sent from uCode to host driver). Unlike Tx, there is only one Rx
1251 : * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
1252 : * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
1253 : * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
1254 : * mapping between RBDs and RBs.
1255 : *
1256 : * Driver must allocate host DRAM memory for the following, and set the
1257 : * physical address of each into device registers:
1258 : *
1259 : * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
1260 : * entries (although any power of 2, up to 4096, is selectable by driver).
1261 : * Each entry (1 dword) points to a receive buffer (RB) of consistent size
1262 : * (typically 4K, although 8K or 16K are also selectable by driver).
1263 : * Driver sets up RB size and number of RBDs in the CB via Rx config
1264 : * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG.
1265 : *
1266 : * Bit fields within one RBD:
1267 : * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1268 : *
1269 : * Driver sets physical address [35:8] of base of RBD circular buffer
1270 : * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1271 : *
1272 : * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
1273 : * (RBs) have been filled, via a "write pointer", actually the index of
1274 : * the RB's corresponding RBD within the circular buffer. Driver sets
1275 : * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1276 : *
1277 : * Bit fields in lower dword of Rx status buffer (upper dword not used
1278 : * by driver:
1279 : * 31-12: Not used by driver
1280 : * 11- 0: Index of last filled Rx buffer descriptor
1281 : * (device writes, driver reads this value)
1282 : *
1283 : * As the driver prepares Receive Buffers (RBs) for device to fill, driver must
1284 : * enter pointers to these RBs into contiguous RBD circular buffer entries,
1285 : * and update the device's "write" index register,
1286 : * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
1287 : *
1288 : * This "write" index corresponds to the *next* RBD that the driver will make
1289 : * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1290 : * the circular buffer. This value should initially be 0 (before preparing any
1291 : * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1292 : * wrap back to 0 at the end of the circular buffer (but don't wrap before
1293 : * "read" index has advanced past 1! See below).
1294 : * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
1295 : *
1296 : * As the device fills RBs (referenced from contiguous RBDs within the circular
1297 : * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1298 : * to tell the driver the index of the latest filled RBD. The driver must
1299 : * read this "read" index from DRAM after receiving an Rx interrupt from device
1300 : *
1301 : * The driver must also internally keep track of a third index, which is the
1302 : * next RBD to process. When receiving an Rx interrupt, driver should process
1303 : * all filled but unprocessed RBs up to, but not including, the RB
1304 : * corresponding to the "read" index. For example, if "read" index becomes "1",
1305 : * driver may process the RB pointed to by RBD 0. Depending on volume of
1306 : * traffic, there may be many RBs to process.
1307 : *
1308 : * If read index == write index, device thinks there is no room to put new data.
1309 : * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1310 : * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1311 : * and "read" indexes; that is, make sure that there are no more than 254
1312 : * buffers waiting to be filled.
1313 : */
1314 : #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0)
1315 : #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1316 : #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND)
1317 :
1318 : /**
1319 : * Physical base address of 8-byte Rx Status buffer.
1320 : * Bit fields:
1321 : * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1322 : */
1323 : #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0)
1324 :
1325 : /**
1326 : * Physical base address of Rx Buffer Descriptor Circular Buffer.
1327 : * Bit fields:
1328 : * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1329 : */
1330 : #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004)
1331 :
1332 : /**
1333 : * Rx write pointer (index, really!).
1334 : * Bit fields:
1335 : * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1336 : * NOTE: For 256-entry circular buffer, use only bits [7:0].
1337 : */
1338 : #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008)
1339 : #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
1340 :
1341 : #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c)
1342 : #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG
1343 :
1344 : /**
1345 : * Rx Config/Status Registers (RCSR)
1346 : * Rx Config Reg for channel 0 (only channel used)
1347 : *
1348 : * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1349 : * normal operation (see bit fields).
1350 : *
1351 : * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1352 : * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for
1353 : * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1354 : *
1355 : * Bit fields:
1356 : * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1357 : * '10' operate normally
1358 : * 29-24: reserved
1359 : * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1360 : * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1361 : * 19-18: reserved
1362 : * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1363 : * '10' 12K, '11' 16K.
1364 : * 15-14: reserved
1365 : * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1366 : * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1367 : * typical value 0x10 (about 1/2 msec)
1368 : * 3- 0: reserved
1369 : */
1370 : #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1371 : #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0)
1372 : #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND)
1373 :
1374 : #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0)
1375 : #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8)
1376 : #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10)
1377 :
1378 : #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1379 : #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
1380 : #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1381 : #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1382 : #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1383 : #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
1384 :
1385 : #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1386 : #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1387 : #define IWM_RX_RB_TIMEOUT (0x11)
1388 :
1389 : #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1390 : #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1391 : #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1392 :
1393 : #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1394 : #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1395 : #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1396 : #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1397 :
1398 : #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1399 : #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1400 : #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1401 :
1402 : /**
1403 : * Rx Shared Status Registers (RSSR)
1404 : *
1405 : * After stopping Rx DMA channel (writing 0 to
1406 : * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1407 : * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1408 : *
1409 : * Bit fields:
1410 : * 24: 1 = Channel 0 is idle
1411 : *
1412 : * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1413 : * contain default values that should not be altered by the driver.
1414 : */
1415 : #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40)
1416 : #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1417 :
1418 : #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND)
1419 : #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004)
1420 : #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1421 : (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008)
1422 :
1423 : #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1424 :
1425 : #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1426 :
1427 : /* TFDB Area - TFDs buffer table */
1428 : #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1429 : #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900)
1430 : #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958)
1431 : #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1432 : #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1433 :
1434 : /**
1435 : * Transmit DMA Channel Control/Status Registers (TCSR)
1436 : *
1437 : * Device has one configuration register for each of 8 Tx DMA/FIFO channels
1438 : * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1439 : * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1440 : *
1441 : * To use a Tx DMA channel, driver must initialize its
1442 : * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1443 : *
1444 : * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1445 : * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1446 : *
1447 : * All other bits should be 0.
1448 : *
1449 : * Bit fields:
1450 : * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1451 : * '10' operate normally
1452 : * 29- 4: Reserved, set to "0"
1453 : * 3: Enable internal DMA requests (1, normal operation), disable (0)
1454 : * 2- 0: Reserved, set to "0"
1455 : */
1456 : #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1457 : #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60)
1458 :
1459 : /* Find Control/Status reg for given Tx DMA/FIFO channel */
1460 : #define IWM_FH_TCSR_CHNL_NUM (8)
1461 :
1462 : /* TCSR: tx_config register values */
1463 : #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1464 : (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1465 : #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1466 : (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1467 : #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1468 : (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1469 :
1470 : #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1471 : #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1472 :
1473 : #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1474 : #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1475 :
1476 : #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1477 : #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1478 : #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1479 :
1480 : #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1481 : #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1482 : #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1483 :
1484 : #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1485 : #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1486 : #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1487 :
1488 : #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1489 : #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1490 : #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1491 :
1492 : #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1493 : #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1494 :
1495 : /**
1496 : * Tx Shared Status Registers (TSSR)
1497 : *
1498 : * After stopping Tx DMA channel (writing 0 to
1499 : * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1500 : * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
1501 : * (channel's buffers empty | no pending requests).
1502 : *
1503 : * Bit fields:
1504 : * 31-24: 1 = Channel buffers empty (channel 7:0)
1505 : * 23-16: 1 = No pending requests (channel 7:0)
1506 : */
1507 : #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0)
1508 : #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0)
1509 :
1510 : #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010)
1511 :
1512 : /**
1513 : * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1514 : * 31: Indicates an address error when accessed to internal memory
1515 : * uCode/driver must write "1" in order to clear this flag
1516 : * 30: Indicates that Host did not send the expected number of dwords to FH
1517 : * uCode/driver must write "1" in order to clear this flag
1518 : * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1519 : * command was received from the scheduler while the TRB was already full
1520 : * with previous command
1521 : * uCode/driver must write "1" in order to clear this flag
1522 : * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1523 : * bit is set, it indicates that the FH has received a full indication
1524 : * from the RTC TxFIFO and the current value of the TxCredit counter was
1525 : * not equal to zero. This mean that the credit mechanism was not
1526 : * synchronized to the TxFIFO status
1527 : * uCode/driver must write "1" in order to clear this flag
1528 : */
1529 : #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018)
1530 : #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008)
1531 :
1532 : #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1533 :
1534 : /* Tx service channels */
1535 : #define IWM_FH_SRVC_CHNL (9)
1536 : #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8)
1537 : #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1538 : #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1539 : (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1540 :
1541 : #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98)
1542 : #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \
1543 : (_chan) * 4)
1544 :
1545 : /* Instruct FH to increment the retry count of a packet when
1546 : * it is brought from the memory to TX-FIFO
1547 : */
1548 : #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1549 :
1550 : #define IWM_RX_QUEUE_SIZE 256
1551 : #define IWM_RX_QUEUE_MASK 255
1552 : #define IWM_RX_QUEUE_SIZE_LOG 8
1553 :
1554 : /*
1555 : * RX related structures and functions
1556 : */
1557 : #define IWM_RX_FREE_BUFFERS 64
1558 : #define IWM_RX_LOW_WATERMARK 8
1559 :
1560 : /**
1561 : * struct iwm_rb_status - reseve buffer status
1562 : * host memory mapped FH registers
1563 : * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
1564 : * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
1565 : * @finished_rb_num [0:11] - Indicates the index of the current RB
1566 : * in which the last frame was written to
1567 : * @finished_fr_num [0:11] - Indicates the index of the RX Frame
1568 : * which was transferred
1569 : */
1570 : struct iwm_rb_status {
1571 : uint16_t closed_rb_num;
1572 : uint16_t closed_fr_num;
1573 : uint16_t finished_rb_num;
1574 : uint16_t finished_fr_nam;
1575 : uint32_t unused;
1576 : } __packed;
1577 :
1578 :
1579 : #define IWM_TFD_QUEUE_SIZE_MAX (256)
1580 : #define IWM_TFD_QUEUE_SIZE_BC_DUP (64)
1581 : #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \
1582 : IWM_TFD_QUEUE_SIZE_BC_DUP)
1583 : #define IWM_TX_DMA_MASK DMA_BIT_MASK(36)
1584 : #define IWM_NUM_OF_TBS 20
1585 :
1586 0 : static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr)
1587 : {
1588 0 : return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF;
1589 : }
1590 : /**
1591 : * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor
1592 : *
1593 : * This structure contains dma address and length of transmission address
1594 : *
1595 : * @lo: low [31:0] portion of the dma address of TX buffer
1596 : * every even is unaligned on 16 bit boundary
1597 : * @hi_n_len 0-3 [35:32] portion of dma
1598 : * 4-15 length of the tx buffer
1599 : */
1600 : struct iwm_tfd_tb {
1601 : uint32_t lo;
1602 : uint16_t hi_n_len;
1603 : } __packed;
1604 :
1605 : /**
1606 : * struct iwm_tfd
1607 : *
1608 : * Transmit Frame Descriptor (TFD)
1609 : *
1610 : * @ __reserved1[3] reserved
1611 : * @ num_tbs 0-4 number of active tbs
1612 : * 5 reserved
1613 : * 6-7 padding (not used)
1614 : * @ tbs[20] transmit frame buffer descriptors
1615 : * @ __pad padding
1616 : *
1617 : * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
1618 : * Both driver and device share these circular buffers, each of which must be
1619 : * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
1620 : *
1621 : * Driver must indicate the physical address of the base of each
1622 : * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers.
1623 : *
1624 : * Each TFD contains pointer/size information for up to 20 data buffers
1625 : * in host DRAM. These buffers collectively contain the (one) frame described
1626 : * by the TFD. Each buffer must be a single contiguous block of memory within
1627 : * itself, but buffers may be scattered in host DRAM. Each buffer has max size
1628 : * of (4K - 4). The concatenates all of a TFD's buffers into a single
1629 : * Tx frame, up to 8 KBytes in size.
1630 : *
1631 : * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
1632 : */
1633 : struct iwm_tfd {
1634 : uint8_t __reserved1[3];
1635 : uint8_t num_tbs;
1636 : struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS];
1637 : uint32_t __pad;
1638 : } __packed;
1639 :
1640 : /* Keep Warm Size */
1641 : #define IWM_KW_SIZE 0x1000 /* 4k */
1642 :
1643 : /* Fixed (non-configurable) rx data from phy */
1644 :
1645 : /**
1646 : * struct iwm_agn_schedq_bc_tbl scheduler byte count table
1647 : * base physical address provided by IWM_SCD_DRAM_BASE_ADDR
1648 : * @tfd_offset 0-12 - tx command byte count
1649 : * 12-16 - station index
1650 : */
1651 : struct iwm_agn_scd_bc_tbl {
1652 : uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE];
1653 : } __packed;
1654 :
1655 : /* Maximum number of Tx queues. */
1656 : #define IWM_MAX_QUEUES 31
1657 :
1658 : /* Tx queue numbers */
1659 : #define IWM_OFFCHANNEL_QUEUE 8
1660 : #define IWM_CMD_QUEUE 9
1661 : #define IWM_AUX_QUEUE 15
1662 :
1663 : #define IWM_TX_FIFO_BK 0
1664 : #define IWM_TX_FIFO_BE 1
1665 : #define IWM_TX_FIFO_VI 2
1666 : #define IWM_TX_FIFO_VO 3
1667 : #define IWM_TX_FIFO_MCAST 5
1668 : #define IWM_TX_FIFO_CMD 7
1669 :
1670 : #define IWM_STATION_COUNT 16
1671 :
1672 : /*
1673 : * Commands
1674 : */
1675 : #define IWM_ALIVE 0x1
1676 : #define IWM_REPLY_ERROR 0x2
1677 : #define IWM_INIT_COMPLETE_NOTIF 0x4
1678 :
1679 : /* PHY context commands */
1680 : #define IWM_PHY_CONTEXT_CMD 0x8
1681 : #define IWM_DBG_CFG 0x9
1682 :
1683 : /* UMAC scan commands */
1684 : #define IWM_SCAN_ITERATION_COMPLETE_UMAC 0xb5
1685 : #define IWM_SCAN_CFG_CMD 0xc
1686 : #define IWM_SCAN_REQ_UMAC 0xd
1687 : #define IWM_SCAN_ABORT_UMAC 0xe
1688 : #define IWM_SCAN_COMPLETE_UMAC 0xf
1689 :
1690 : /* station table */
1691 : #define IWM_ADD_STA_KEY 0x17
1692 : #define IWM_ADD_STA 0x18
1693 : #define IWM_REMOVE_STA 0x19
1694 :
1695 : /* TX */
1696 : #define IWM_TX_CMD 0x1c
1697 : #define IWM_TXPATH_FLUSH 0x1e
1698 : #define IWM_MGMT_MCAST_KEY 0x1f
1699 :
1700 : /* scheduler config */
1701 : #define IWM_SCD_QUEUE_CFG 0x1d
1702 :
1703 : /* global key */
1704 : #define IWM_WEP_KEY 0x20
1705 :
1706 : /* MAC and Binding commands */
1707 : #define IWM_MAC_CONTEXT_CMD 0x28
1708 : #define IWM_TIME_EVENT_CMD 0x29 /* both CMD and response */
1709 : #define IWM_TIME_EVENT_NOTIFICATION 0x2a
1710 : #define IWM_BINDING_CONTEXT_CMD 0x2b
1711 : #define IWM_TIME_QUOTA_CMD 0x2c
1712 : #define IWM_NON_QOS_TX_COUNTER_CMD 0x2d
1713 :
1714 : #define IWM_LQ_CMD 0x4e
1715 :
1716 : /* Calibration */
1717 : #define IWM_TEMPERATURE_NOTIFICATION 0x62
1718 : #define IWM_CALIBRATION_CFG_CMD 0x65
1719 : #define IWM_CALIBRATION_RES_NOTIFICATION 0x66
1720 : #define IWM_CALIBRATION_COMPLETE_NOTIFICATION 0x67
1721 : #define IWM_RADIO_VERSION_NOTIFICATION 0x68
1722 :
1723 : /* Scan offload */
1724 : #define IWM_SCAN_OFFLOAD_REQUEST_CMD 0x51
1725 : #define IWM_SCAN_OFFLOAD_ABORT_CMD 0x52
1726 : #define IWM_HOT_SPOT_CMD 0x53
1727 : #define IWM_SCAN_OFFLOAD_COMPLETE 0x6d
1728 : #define IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD 0x6e
1729 : #define IWM_SCAN_OFFLOAD_CONFIG_CMD 0x6f
1730 : #define IWM_MATCH_FOUND_NOTIFICATION 0xd9
1731 : #define IWM_SCAN_ITERATION_COMPLETE 0xe7
1732 :
1733 : /* Phy */
1734 : #define IWM_PHY_CONFIGURATION_CMD 0x6a
1735 : #define IWM_CALIB_RES_NOTIF_PHY_DB 0x6b
1736 : /* IWM_PHY_DB_CMD 0x6c */
1737 :
1738 : /* Power - legacy power table command */
1739 : #define IWM_POWER_TABLE_CMD 0x77
1740 : #define IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION 0x78
1741 :
1742 : /* Thermal Throttling*/
1743 : #define IWM_REPLY_THERMAL_MNG_BACKOFF 0x7e
1744 :
1745 : /* NVM */
1746 : #define IWM_NVM_ACCESS_CMD 0x88
1747 :
1748 : #define IWM_SET_CALIB_DEFAULT_CMD 0x8e
1749 :
1750 : #define IWM_BEACON_NOTIFICATION 0x90
1751 : #define IWM_BEACON_TEMPLATE_CMD 0x91
1752 : #define IWM_TX_ANT_CONFIGURATION_CMD 0x98
1753 : #define IWM_BT_CONFIG 0x9b
1754 : #define IWM_STATISTICS_NOTIFICATION 0x9d
1755 : #define IWM_REDUCE_TX_POWER_CMD 0x9f
1756 :
1757 : /* RF-KILL commands and notifications */
1758 : #define IWM_CARD_STATE_CMD 0xa0
1759 : #define IWM_CARD_STATE_NOTIFICATION 0xa1
1760 :
1761 : #define IWM_MISSED_BEACONS_NOTIFICATION 0xa2
1762 :
1763 : #define IWM_MFUART_LOAD_NOTIFICATION 0xb1
1764 :
1765 : /* Power - new power table command */
1766 : #define IWM_MAC_PM_POWER_TABLE 0xa9
1767 :
1768 : #define IWM_REPLY_RX_PHY_CMD 0xc0
1769 : #define IWM_REPLY_RX_MPDU_CMD 0xc1
1770 : #define IWM_BA_NOTIF 0xc5
1771 :
1772 : /* Location Aware Regulatory */
1773 : #define IWM_MCC_UPDATE_CMD 0xc8
1774 : #define IWM_MCC_CHUB_UPDATE_CMD 0xc9
1775 :
1776 : /* BT Coex */
1777 : #define IWM_BT_COEX_PRIO_TABLE 0xcc
1778 : #define IWM_BT_COEX_PROT_ENV 0xcd
1779 : #define IWM_BT_PROFILE_NOTIFICATION 0xce
1780 : #define IWM_BT_COEX_CI 0x5d
1781 :
1782 : #define IWM_REPLY_SF_CFG_CMD 0xd1
1783 : #define IWM_REPLY_BEACON_FILTERING_CMD 0xd2
1784 :
1785 : /* DTS measurements */
1786 : #define IWM_CMD_DTS_MEASUREMENT_TRIGGER 0xdc
1787 : #define IWM_DTS_MEASUREMENT_NOTIFICATION 0xdd
1788 :
1789 : #define IWM_REPLY_DEBUG_CMD 0xf0
1790 : #define IWM_DEBUG_LOG_MSG 0xf7
1791 :
1792 : #define IWM_MCAST_FILTER_CMD 0xd0
1793 :
1794 : /* D3 commands/notifications */
1795 : #define IWM_D3_CONFIG_CMD 0xd3
1796 : #define IWM_PROT_OFFLOAD_CONFIG_CMD 0xd4
1797 : #define IWM_OFFLOADS_QUERY_CMD 0xd5
1798 : #define IWM_REMOTE_WAKE_CONFIG_CMD 0xd6
1799 :
1800 : /* for WoWLAN in particular */
1801 : #define IWM_WOWLAN_PATTERNS 0xe0
1802 : #define IWM_WOWLAN_CONFIGURATION 0xe1
1803 : #define IWM_WOWLAN_TSC_RSC_PARAM 0xe2
1804 : #define IWM_WOWLAN_TKIP_PARAM 0xe3
1805 : #define IWM_WOWLAN_KEK_KCK_MATERIAL 0xe4
1806 : #define IWM_WOWLAN_GET_STATUSES 0xe5
1807 : #define IWM_WOWLAN_TX_POWER_PER_DB 0xe6
1808 :
1809 : /* and for NetDetect */
1810 : #define IWM_NET_DETECT_CONFIG_CMD 0x54
1811 : #define IWM_NET_DETECT_PROFILES_QUERY_CMD 0x56
1812 : #define IWM_NET_DETECT_PROFILES_CMD 0x57
1813 : #define IWM_NET_DETECT_HOTSPOTS_CMD 0x58
1814 : #define IWM_NET_DETECT_HOTSPOTS_QUERY_CMD 0x59
1815 :
1816 : /* system group command IDs */
1817 : #define IWM_FSEQ_VER_MISMATCH_NOTIFICATION 0xff
1818 :
1819 : #define IWM_REPLY_MAX 0xff
1820 :
1821 : /**
1822 : * struct iwm_cmd_response - generic response struct for most commands
1823 : * @status: status of the command asked, changes for each one
1824 : */
1825 : struct iwm_cmd_response {
1826 : uint32_t status;
1827 : };
1828 :
1829 : /*
1830 : * struct iwm_tx_ant_cfg_cmd
1831 : * @valid: valid antenna configuration
1832 : */
1833 : struct iwm_tx_ant_cfg_cmd {
1834 : uint32_t valid;
1835 : } __packed;
1836 :
1837 : /**
1838 : * struct iwm_reduce_tx_power_cmd - TX power reduction command
1839 : * IWM_REDUCE_TX_POWER_CMD = 0x9f
1840 : * @flags: (reserved for future implementation)
1841 : * @mac_context_id: id of the mac ctx for which we are reducing TX power.
1842 : * @pwr_restriction: TX power restriction in dBms.
1843 : */
1844 : struct iwm_reduce_tx_power_cmd {
1845 : uint8_t flags;
1846 : uint8_t mac_context_id;
1847 : uint16_t pwr_restriction;
1848 : } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */
1849 :
1850 : /*
1851 : * Calibration control struct.
1852 : * Sent as part of the phy configuration command.
1853 : * @flow_trigger: bitmap for which calibrations to perform according to
1854 : * flow triggers.
1855 : * @event_trigger: bitmap for which calibrations to perform according to
1856 : * event triggers.
1857 : */
1858 : struct iwm_calib_ctrl {
1859 : uint32_t flow_trigger;
1860 : uint32_t event_trigger;
1861 : } __packed;
1862 :
1863 : /* This defines the bitmap of various calibrations to enable in both
1864 : * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD.
1865 : */
1866 : #define IWM_CALIB_CFG_XTAL_IDX (1 << 0)
1867 : #define IWM_CALIB_CFG_TEMPERATURE_IDX (1 << 1)
1868 : #define IWM_CALIB_CFG_VOLTAGE_READ_IDX (1 << 2)
1869 : #define IWM_CALIB_CFG_PAPD_IDX (1 << 3)
1870 : #define IWM_CALIB_CFG_TX_PWR_IDX (1 << 4)
1871 : #define IWM_CALIB_CFG_DC_IDX (1 << 5)
1872 : #define IWM_CALIB_CFG_BB_FILTER_IDX (1 << 6)
1873 : #define IWM_CALIB_CFG_LO_LEAKAGE_IDX (1 << 7)
1874 : #define IWM_CALIB_CFG_TX_IQ_IDX (1 << 8)
1875 : #define IWM_CALIB_CFG_TX_IQ_SKEW_IDX (1 << 9)
1876 : #define IWM_CALIB_CFG_RX_IQ_IDX (1 << 10)
1877 : #define IWM_CALIB_CFG_RX_IQ_SKEW_IDX (1 << 11)
1878 : #define IWM_CALIB_CFG_SENSITIVITY_IDX (1 << 12)
1879 : #define IWM_CALIB_CFG_CHAIN_NOISE_IDX (1 << 13)
1880 : #define IWM_CALIB_CFG_DISCONNECTED_ANT_IDX (1 << 14)
1881 : #define IWM_CALIB_CFG_ANT_COUPLING_IDX (1 << 15)
1882 : #define IWM_CALIB_CFG_DAC_IDX (1 << 16)
1883 : #define IWM_CALIB_CFG_ABS_IDX (1 << 17)
1884 : #define IWM_CALIB_CFG_AGC_IDX (1 << 18)
1885 :
1886 : /*
1887 : * Phy configuration command.
1888 : */
1889 : struct iwm_phy_cfg_cmd {
1890 : uint32_t phy_cfg;
1891 : struct iwm_calib_ctrl calib_control;
1892 : } __packed;
1893 :
1894 : #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1))
1895 : #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3))
1896 : #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5))
1897 : #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7))
1898 : #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8)
1899 : #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9)
1900 : #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10)
1901 : #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12)
1902 : #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13)
1903 : #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14)
1904 :
1905 : /*
1906 : * PHY db
1907 : */
1908 :
1909 : #define IWM_PHY_DB_CFG 1
1910 : #define IWM_PHY_DB_CALIB_NCH 2
1911 : #define IWM_PHY_DB_UNUSED 3
1912 : #define IWM_PHY_DB_CALIB_CHG_PAPD 4
1913 : #define IWM_PHY_DB_CALIB_CHG_TXP 5
1914 : #define IWM_PHY_DB_MAX 6
1915 :
1916 : #define IWM_PHY_DB_CMD 0x6c /* TEMP API - The actual is 0x8c */
1917 :
1918 : /*
1919 : * phy db - configure operational ucode
1920 : */
1921 : struct iwm_phy_db_cmd {
1922 : uint16_t type;
1923 : uint16_t length;
1924 : uint8_t data[];
1925 : } __packed;
1926 :
1927 : /* for parsing of tx power channel group data that comes from the firmware*/
1928 : struct iwm_phy_db_chg_txp {
1929 : uint32_t space;
1930 : uint16_t max_channel_idx;
1931 : } __packed;
1932 :
1933 : /*
1934 : * phy db - Receive phy db chunk after calibrations
1935 : */
1936 : struct iwm_calib_res_notif_phy_db {
1937 : uint16_t type;
1938 : uint16_t length;
1939 : uint8_t data[];
1940 : } __packed;
1941 :
1942 : /* 7k family NVM HW-Section offset (in words) definitions */
1943 : #define IWM_HW_ADDR 0x15
1944 : /* 7k family NVM SW-Section offset (in words) definitions */
1945 : #define IWM_NVM_SW_SECTION 0x1C0
1946 : #define IWM_NVM_VERSION 0
1947 : #define IWM_RADIO_CFG 1
1948 : #define IWM_SKU 2
1949 : #define IWM_N_HW_ADDRS 3
1950 : #define IWM_NVM_CHANNELS 0x1E0 - IWM_NVM_SW_SECTION
1951 : /* 7k family NVM calibration section offset (in words) definitions */
1952 : #define IWM_NVM_CALIB_SECTION 0x2B8
1953 : #define IWM_XTAL_CALIB (0x316 - IWM_NVM_CALIB_SECTION)
1954 :
1955 : /* 8k family NVM HW-Section offset (in words) definitions */
1956 : #define IWM_HW_ADDR0_WFPM_8000 0x12
1957 : #define IWM_HW_ADDR1_WFPM_8000 0x16
1958 : #define IWM_HW_ADDR0_PCIE_8000 0x8A
1959 : #define IWM_HW_ADDR1_PCIE_8000 0x8E
1960 : #define IWM_MAC_ADDRESS_OVERRIDE_8000 1
1961 :
1962 : /* 8k family NVM SW-Section offset (in words) definitions */
1963 : #define IWM_NVM_SW_SECTION_8000 0x1C0
1964 : #define IWM_NVM_VERSION_8000 0
1965 : #define IWM_RADIO_CFG_8000 0
1966 : #define IWM_SKU_8000 2
1967 : #define IWM_N_HW_ADDRS_8000 3
1968 :
1969 : /* 8k family NVM REGULATORY -Section offset (in words) definitions */
1970 : #define IWM_NVM_CHANNELS_8000 0
1971 : #define IWM_NVM_LAR_OFFSET_8000_OLD 0x4C7
1972 : #define IWM_NVM_LAR_OFFSET_8000 0x507
1973 : #define IWM_NVM_LAR_ENABLED_8000 0x7
1974 :
1975 : /* 8k family NVM calibration section offset (in words) definitions */
1976 : #define IWM_NVM_CALIB_SECTION_8000 0x2B8
1977 : #define IWM_XTAL_CALIB_8000 (0x316 - IWM_NVM_CALIB_SECTION_8000)
1978 :
1979 : /* SKU Capabilities (actual values from NVM definition) */
1980 : #define IWM_NVM_SKU_CAP_BAND_24GHZ (1 << 0)
1981 : #define IWM_NVM_SKU_CAP_BAND_52GHZ (1 << 1)
1982 : #define IWM_NVM_SKU_CAP_11N_ENABLE (1 << 2)
1983 : #define IWM_NVM_SKU_CAP_11AC_ENABLE (1 << 3)
1984 : #define IWM_NVM_SKU_CAP_MIMO_DISABLE (1 << 5)
1985 :
1986 : /* radio config bits (actual values from NVM definition) */
1987 : #define IWM_NVM_RF_CFG_DASH_MSK(x) (x & 0x3) /* bits 0-1 */
1988 : #define IWM_NVM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
1989 : #define IWM_NVM_RF_CFG_TYPE_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
1990 : #define IWM_NVM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
1991 : #define IWM_NVM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
1992 : #define IWM_NVM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
1993 :
1994 : #define IWM_NVM_RF_CFG_PNUM_MSK_8000(x) (x & 0xF)
1995 : #define IWM_NVM_RF_CFG_DASH_MSK_8000(x) ((x >> 4) & 0xF)
1996 : #define IWM_NVM_RF_CFG_STEP_MSK_8000(x) ((x >> 8) & 0xF)
1997 : #define IWM_NVM_RF_CFG_TYPE_MSK_8000(x) ((x >> 12) & 0xFFF)
1998 : #define IWM_NVM_RF_CFG_TX_ANT_MSK_8000(x) ((x >> 24) & 0xF)
1999 : #define IWM_NVM_RF_CFG_RX_ANT_MSK_8000(x) ((x >> 28) & 0xF)
2000 :
2001 : #define DEFAULT_MAX_TX_POWER 16
2002 :
2003 : /*
2004 : * channel flags in NVM
2005 : * @IWM_NVM_CHANNEL_VALID: channel is usable for this SKU/geo
2006 : * @IWM_NVM_CHANNEL_IBSS: usable as an IBSS channel
2007 : * @IWM_NVM_CHANNEL_ACTIVE: active scanning allowed
2008 : * @IWM_NVM_CHANNEL_RADAR: radar detection required
2009 : * @IWM_NVM_CHANNEL_DFS: dynamic freq selection candidate
2010 : * @IWM_NVM_CHANNEL_WIDE: 20 MHz channel okay (?)
2011 : * @IWM_NVM_CHANNEL_40MHZ: 40 MHz channel okay (?)
2012 : * @IWM_NVM_CHANNEL_80MHZ: 80 MHz channel okay (?)
2013 : * @IWM_NVM_CHANNEL_160MHZ: 160 MHz channel okay (?)
2014 : */
2015 : #define IWM_NVM_CHANNEL_VALID (1 << 0)
2016 : #define IWM_NVM_CHANNEL_IBSS (1 << 1)
2017 : #define IWM_NVM_CHANNEL_ACTIVE (1 << 3)
2018 : #define IWM_NVM_CHANNEL_RADAR (1 << 4)
2019 : #define IWM_NVM_CHANNEL_DFS (1 << 7)
2020 : #define IWM_NVM_CHANNEL_WIDE (1 << 8)
2021 : #define IWM_NVM_CHANNEL_40MHZ (1 << 9)
2022 : #define IWM_NVM_CHANNEL_80MHZ (1 << 10)
2023 : #define IWM_NVM_CHANNEL_160MHZ (1 << 11)
2024 :
2025 : /* Target of the IWM_NVM_ACCESS_CMD */
2026 : #define IWM_NVM_ACCESS_TARGET_CACHE 0
2027 : #define IWM_NVM_ACCESS_TARGET_OTP 1
2028 : #define IWM_NVM_ACCESS_TARGET_EEPROM 2
2029 :
2030 : /* Section types for IWM_NVM_ACCESS_CMD */
2031 : #define IWM_NVM_SECTION_TYPE_HW 0
2032 : #define IWM_NVM_SECTION_TYPE_SW 1
2033 : #define IWM_NVM_SECTION_TYPE_PAPD 2
2034 : #define IWM_NVM_SECTION_TYPE_REGULATORY 3
2035 : #define IWM_NVM_SECTION_TYPE_CALIBRATION 4
2036 : #define IWM_NVM_SECTION_TYPE_PRODUCTION 5
2037 : #define IWM_NVM_SECTION_TYPE_POST_FCS_CALIB 6
2038 : /* 7, 8, 9 unknown */
2039 : #define IWM_NVM_SECTION_TYPE_HW_8000 10
2040 : #define IWM_NVM_SECTION_TYPE_MAC_OVERRIDE 11
2041 : #define IWM_NVM_SECTION_TYPE_PHY_SKU 12
2042 : #define IWM_NVM_NUM_OF_SECTIONS 13
2043 :
2044 : /**
2045 : * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section
2046 : * @op_code: 0 - read, 1 - write
2047 : * @target: IWM_NVM_ACCESS_TARGET_*
2048 : * @type: IWM_NVM_SECTION_TYPE_*
2049 : * @offset: offset in bytes into the section
2050 : * @length: in bytes, to read/write
2051 : * @data: if write operation, the data to write. On read its empty
2052 : */
2053 : struct iwm_nvm_access_cmd {
2054 : uint8_t op_code;
2055 : uint8_t target;
2056 : uint16_t type;
2057 : uint16_t offset;
2058 : uint16_t length;
2059 : uint8_t data[];
2060 : } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */
2061 :
2062 : /**
2063 : * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD
2064 : * @offset: offset in bytes into the section
2065 : * @length: in bytes, either how much was written or read
2066 : * @type: IWM_NVM_SECTION_TYPE_*
2067 : * @status: 0 for success, fail otherwise
2068 : * @data: if read operation, the data returned. Empty on write.
2069 : */
2070 : struct iwm_nvm_access_resp {
2071 : uint16_t offset;
2072 : uint16_t length;
2073 : uint16_t type;
2074 : uint16_t status;
2075 : uint8_t data[];
2076 : } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */
2077 :
2078 : /* IWM_ALIVE 0x1 */
2079 :
2080 : /* alive response is_valid values */
2081 : #define IWM_ALIVE_RESP_UCODE_OK (1 << 0)
2082 : #define IWM_ALIVE_RESP_RFKILL (1 << 1)
2083 :
2084 : /* alive response ver_type values */
2085 : #define IWM_FW_TYPE_HW 0
2086 : #define IWM_FW_TYPE_PROT 1
2087 : #define IWM_FW_TYPE_AP 2
2088 : #define IWM_FW_TYPE_WOWLAN 3
2089 : #define IWM_FW_TYPE_TIMING 4
2090 : #define IWM_FW_TYPE_WIPAN 5
2091 :
2092 : /* alive response ver_subtype values */
2093 : #define IWM_FW_SUBTYPE_FULL_FEATURE 0
2094 : #define IWM_FW_SUBTYPE_BOOTSRAP 1 /* Not valid */
2095 : #define IWM_FW_SUBTYPE_REDUCED 2
2096 : #define IWM_FW_SUBTYPE_ALIVE_ONLY 3
2097 : #define IWM_FW_SUBTYPE_WOWLAN 4
2098 : #define IWM_FW_SUBTYPE_AP_SUBTYPE 5
2099 : #define IWM_FW_SUBTYPE_WIPAN 6
2100 : #define IWM_FW_SUBTYPE_INITIALIZE 9
2101 :
2102 : #define IWM_ALIVE_STATUS_ERR 0xDEAD
2103 : #define IWM_ALIVE_STATUS_OK 0xCAFE
2104 :
2105 : #define IWM_ALIVE_FLG_RFKILL (1 << 0)
2106 :
2107 : struct iwm_alive_resp_v1 {
2108 : uint16_t status;
2109 : uint16_t flags;
2110 : uint8_t ucode_minor;
2111 : uint8_t ucode_major;
2112 : uint16_t id;
2113 : uint8_t api_minor;
2114 : uint8_t api_major;
2115 : uint8_t ver_subtype;
2116 : uint8_t ver_type;
2117 : uint8_t mac;
2118 : uint8_t opt;
2119 : uint16_t reserved2;
2120 : uint32_t timestamp;
2121 : uint32_t error_event_table_ptr; /* SRAM address for error log */
2122 : uint32_t log_event_table_ptr; /* SRAM address for event log */
2123 : uint32_t cpu_register_ptr;
2124 : uint32_t dbgm_config_ptr;
2125 : uint32_t alive_counter_ptr;
2126 : uint32_t scd_base_ptr; /* SRAM address for SCD */
2127 : } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */
2128 :
2129 : struct iwm_alive_resp_v2 {
2130 : uint16_t status;
2131 : uint16_t flags;
2132 : uint8_t ucode_minor;
2133 : uint8_t ucode_major;
2134 : uint16_t id;
2135 : uint8_t api_minor;
2136 : uint8_t api_major;
2137 : uint8_t ver_subtype;
2138 : uint8_t ver_type;
2139 : uint8_t mac;
2140 : uint8_t opt;
2141 : uint16_t reserved2;
2142 : uint32_t timestamp;
2143 : uint32_t error_event_table_ptr; /* SRAM address for error log */
2144 : uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */
2145 : uint32_t cpu_register_ptr;
2146 : uint32_t dbgm_config_ptr;
2147 : uint32_t alive_counter_ptr;
2148 : uint32_t scd_base_ptr; /* SRAM address for SCD */
2149 : uint32_t st_fwrd_addr; /* pointer to Store and forward */
2150 : uint32_t st_fwrd_size;
2151 : uint8_t umac_minor; /* UMAC version: minor */
2152 : uint8_t umac_major; /* UMAC version: major */
2153 : uint16_t umac_id; /* UMAC version: id */
2154 : uint32_t error_info_addr; /* SRAM address for UMAC error log */
2155 : uint32_t dbg_print_buff_addr;
2156 : } __packed; /* ALIVE_RES_API_S_VER_2 */
2157 :
2158 : struct iwm_alive_resp_v3 {
2159 : uint16_t status;
2160 : uint16_t flags;
2161 : uint32_t ucode_minor;
2162 : uint32_t ucode_major;
2163 : uint8_t ver_subtype;
2164 : uint8_t ver_type;
2165 : uint8_t mac;
2166 : uint8_t opt;
2167 : uint32_t timestamp;
2168 : uint32_t error_event_table_ptr; /* SRAM address for error log */
2169 : uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */
2170 : uint32_t cpu_register_ptr;
2171 : uint32_t dbgm_config_ptr;
2172 : uint32_t alive_counter_ptr;
2173 : uint32_t scd_base_ptr; /* SRAM address for SCD */
2174 : uint32_t st_fwrd_addr; /* pointer to Store and forward */
2175 : uint32_t st_fwrd_size;
2176 : uint32_t umac_minor; /* UMAC version: minor */
2177 : uint32_t umac_major; /* UMAC version: major */
2178 : uint32_t error_info_addr; /* SRAM address for UMAC error log */
2179 : uint32_t dbg_print_buff_addr;
2180 : } __packed; /* ALIVE_RES_API_S_VER_3 */
2181 :
2182 : /* Error response/notification */
2183 : #define IWM_FW_ERR_UNKNOWN_CMD 0x0
2184 : #define IWM_FW_ERR_INVALID_CMD_PARAM 0x1
2185 : #define IWM_FW_ERR_SERVICE 0x2
2186 : #define IWM_FW_ERR_ARC_MEMORY 0x3
2187 : #define IWM_FW_ERR_ARC_CODE 0x4
2188 : #define IWM_FW_ERR_WATCH_DOG 0x5
2189 : #define IWM_FW_ERR_WEP_GRP_KEY_INDX 0x10
2190 : #define IWM_FW_ERR_WEP_KEY_SIZE 0x11
2191 : #define IWM_FW_ERR_OBSOLETE_FUNC 0x12
2192 : #define IWM_FW_ERR_UNEXPECTED 0xFE
2193 : #define IWM_FW_ERR_FATAL 0xFF
2194 :
2195 : /**
2196 : * struct iwm_error_resp - FW error indication
2197 : * ( IWM_REPLY_ERROR = 0x2 )
2198 : * @error_type: one of IWM_FW_ERR_*
2199 : * @cmd_id: the command ID for which the error occured
2200 : * @bad_cmd_seq_num: sequence number of the erroneous command
2201 : * @error_service: which service created the error, applicable only if
2202 : * error_type = 2, otherwise 0
2203 : * @timestamp: TSF in usecs.
2204 : */
2205 : struct iwm_error_resp {
2206 : uint32_t error_type;
2207 : uint8_t cmd_id;
2208 : uint8_t reserved1;
2209 : uint16_t bad_cmd_seq_num;
2210 : uint32_t error_service;
2211 : uint64_t timestamp;
2212 : } __packed;
2213 :
2214 :
2215 : /* Common PHY, MAC and Bindings definitions */
2216 :
2217 : #define IWM_MAX_MACS_IN_BINDING (3)
2218 : #define IWM_MAX_BINDINGS (4)
2219 : #define IWM_AUX_BINDING_INDEX (3)
2220 : #define IWM_MAX_PHYS (4)
2221 :
2222 : /* Used to extract ID and color from the context dword */
2223 : #define IWM_FW_CTXT_ID_POS (0)
2224 : #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS)
2225 : #define IWM_FW_CTXT_COLOR_POS (8)
2226 : #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS)
2227 : #define IWM_FW_CTXT_INVALID (0xffffffff)
2228 :
2229 : #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\
2230 : (_color << IWM_FW_CTXT_COLOR_POS))
2231 :
2232 : /* Possible actions on PHYs, MACs and Bindings */
2233 : #define IWM_FW_CTXT_ACTION_STUB 0
2234 : #define IWM_FW_CTXT_ACTION_ADD 1
2235 : #define IWM_FW_CTXT_ACTION_MODIFY 2
2236 : #define IWM_FW_CTXT_ACTION_REMOVE 3
2237 : #define IWM_FW_CTXT_ACTION_NUM 4
2238 : /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
2239 :
2240 : /* Time Events */
2241 :
2242 : /* Time Event types, according to MAC type */
2243 :
2244 : /* BSS Station Events */
2245 : #define IWM_TE_BSS_STA_AGGRESSIVE_ASSOC 0
2246 : #define IWM_TE_BSS_STA_ASSOC 1
2247 : #define IWM_TE_BSS_EAP_DHCP_PROT 2
2248 : #define IWM_TE_BSS_QUIET_PERIOD 3
2249 :
2250 : /* P2P Device Events */
2251 : #define IWM_TE_P2P_DEVICE_DISCOVERABLE 4
2252 : #define IWM_TE_P2P_DEVICE_LISTEN 5
2253 : #define IWM_TE_P2P_DEVICE_ACTION_SCAN 6
2254 : #define IWM_TE_P2P_DEVICE_FULL_SCAN 7
2255 :
2256 : /* P2P Client Events */
2257 : #define IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC 8
2258 : #define IWM_TE_P2P_CLIENT_ASSOC 9
2259 : #define IWM_TE_P2P_CLIENT_QUIET_PERIOD 10
2260 :
2261 : /* P2P GO Events */
2262 : #define IWM_TE_P2P_GO_ASSOC_PROT 11
2263 : #define IWM_TE_P2P_GO_REPETITIVE_NOA 12
2264 : #define IWM_TE_P2P_GO_CT_WINDOW 13
2265 :
2266 : /* WiDi Sync Events */
2267 : #define IWM_TE_WIDI_TX_SYNC 14
2268 :
2269 : #define IWM_TE_MAX 15
2270 : /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */
2271 :
2272 :
2273 :
2274 : /* Time event - defines for command API v1 */
2275 :
2276 : /*
2277 : * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed.
2278 : * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2279 : * the first fragment is scheduled.
2280 : * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only
2281 : * the first 2 fragments are scheduled.
2282 : * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2283 : * number of fragments are valid.
2284 : *
2285 : * Other than the constant defined above, specifying a fragmentation value 'x'
2286 : * means that the event can be fragmented but only the first 'x' will be
2287 : * scheduled.
2288 : */
2289 : #define IWM_TE_V1_FRAG_NONE 0
2290 : #define IWM_TE_V1_FRAG_SINGLE 1
2291 : #define IWM_TE_V1_FRAG_DUAL 2
2292 : #define IWM_TE_V1_FRAG_ENDLESS 0xffffffff
2293 :
2294 : /* If a Time Event can be fragmented, this is the max number of fragments */
2295 : #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff
2296 : /* Repeat the time event endlessly (until removed) */
2297 : #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff
2298 : /* If a Time Event has bounded repetitions, this is the maximal value */
2299 : #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
2300 :
2301 : /* Time Event dependencies: none, on another TE, or in a specific time */
2302 : #define IWM_TE_V1_INDEPENDENT 0
2303 : #define IWM_TE_V1_DEP_OTHER (1 << 0)
2304 : #define IWM_TE_V1_DEP_TSF (1 << 1)
2305 : #define IWM_TE_V1_EVENT_SOCIOPATHIC (1 << 2)
2306 : /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */
2307 :
2308 : /*
2309 : * @IWM_TE_V1_NOTIF_NONE: no notifications
2310 : * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start
2311 : * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end
2312 : * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use
2313 : * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use.
2314 : * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2315 : * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2316 : * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use.
2317 : * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use.
2318 : *
2319 : * Supported Time event notifications configuration.
2320 : * A notification (both event and fragment) includes a status indicating weather
2321 : * the FW was able to schedule the event or not. For fragment start/end
2322 : * notification the status is always success. There is no start/end fragment
2323 : * notification for monolithic events.
2324 : */
2325 : #define IWM_TE_V1_NOTIF_NONE 0
2326 : #define IWM_TE_V1_NOTIF_HOST_EVENT_START (1 << 0)
2327 : #define IWM_TE_V1_NOTIF_HOST_EVENT_END (1 << 1)
2328 : #define IWM_TE_V1_NOTIF_INTERNAL_EVENT_START (1 << 2)
2329 : #define IWM_TE_V1_NOTIF_INTERNAL_EVENT_END (1 << 3)
2330 : #define IWM_TE_V1_NOTIF_HOST_FRAG_START (1 << 4)
2331 : #define IWM_TE_V1_NOTIF_HOST_FRAG_END (1 << 5)
2332 : #define IWM_TE_V1_NOTIF_INTERNAL_FRAG_START (1 << 6)
2333 : #define IWM_TE_V1_NOTIF_INTERNAL_FRAG_END (1 << 7)
2334 : /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */
2335 :
2336 :
2337 : /**
2338 : * struct iwm_time_event_cmd_api_v1 - configuring Time Events
2339 : * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also
2340 : * with version 2. determined by IWM_UCODE_TLV_FLAGS)
2341 : * ( IWM_TIME_EVENT_CMD = 0x29 )
2342 : * @id_and_color: ID and color of the relevant MAC
2343 : * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2344 : * @id: this field has two meanings, depending on the action:
2345 : * If the action is ADD, then it means the type of event to add.
2346 : * For all other actions it is the unique event ID assigned when the
2347 : * event was added by the FW.
2348 : * @apply_time: When to start the Time Event (in GP2)
2349 : * @max_delay: maximum delay to event's start (apply time), in TU
2350 : * @depends_on: the unique ID of the event we depend on (if any)
2351 : * @interval: interval between repetitions, in TU
2352 : * @interval_reciprocal: 2^32 / interval
2353 : * @duration: duration of event in TU
2354 : * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2355 : * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF
2356 : * and IWM_TE_V1_EVENT_SOCIOPATHIC
2357 : * @is_present: 0 or 1, are we present or absent during the Time Event
2358 : * @max_frags: maximal number of fragments the Time Event can be divided to
2359 : * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when)
2360 : */
2361 : struct iwm_time_event_cmd_v1 {
2362 : /* COMMON_INDEX_HDR_API_S_VER_1 */
2363 : uint32_t id_and_color;
2364 : uint32_t action;
2365 : uint32_t id;
2366 : /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */
2367 : uint32_t apply_time;
2368 : uint32_t max_delay;
2369 : uint32_t dep_policy;
2370 : uint32_t depends_on;
2371 : uint32_t is_present;
2372 : uint32_t max_frags;
2373 : uint32_t interval;
2374 : uint32_t interval_reciprocal;
2375 : uint32_t duration;
2376 : uint32_t repeat;
2377 : uint32_t notify;
2378 : } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */
2379 :
2380 :
2381 : /* Time event - defines for command API v2 */
2382 :
2383 : /**
2384 : * DOC: Time Events - what is it?
2385 : *
2386 : * Time Events are a fw feature that allows the driver to control the presence
2387 : * of the device on the channel. Since the fw supports multiple channels
2388 : * concurrently, the fw may choose to jump to another channel at any time.
2389 : * In order to make sure that the fw is on a specific channel at a certain time
2390 : * and for a certain duration, the driver needs to issue a time event.
2391 : *
2392 : * The simplest example is for BSS association. The driver issues a time event,
2393 : * waits for it to start, and only then tells mac80211 that we can start the
2394 : * association. This way, we make sure that the association will be done
2395 : * smoothly and won't be interrupted by channel switch decided within the fw.
2396 : */
2397 :
2398 : /**
2399 : * DOC: The flow against the fw
2400 : *
2401 : * When the driver needs to make sure we are in a certain channel, at a certain
2402 : * time and for a certain duration, it sends a Time Event. The flow against the
2403 : * fw goes like this:
2404 : * 1) Driver sends a TIME_EVENT_CMD to the fw
2405 : * 2) Driver gets the response for that command. This response contains the
2406 : * Unique ID (UID) of the event.
2407 : * 3) The fw sends notification when the event starts.
2408 : *
2409 : * Of course the API provides various options that allow to cover parameters
2410 : * of the flow.
2411 : * What is the duration of the event?
2412 : * What is the start time of the event?
2413 : * Is there an end-time for the event?
2414 : * How much can the event be delayed?
2415 : * Can the event be split?
2416 : * If yes what is the maximal number of chunks?
2417 : * etc...
2418 : */
2419 :
2420 : /*
2421 : * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
2422 : * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2423 : * the first fragment is scheduled.
2424 : * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
2425 : * the first 2 fragments are scheduled.
2426 : * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2427 : * number of fragments are valid.
2428 : *
2429 : * Other than the constant defined above, specifying a fragmentation value 'x'
2430 : * means that the event can be fragmented but only the first 'x' will be
2431 : * scheduled.
2432 : */
2433 : #define IWM_TE_V2_FRAG_NONE 0
2434 : #define IWM_TE_V2_FRAG_SINGLE 1
2435 : #define IWM_TE_V2_FRAG_DUAL 2
2436 : #define IWM_TE_V2_FRAG_MAX 0xfe
2437 : #define IWM_TE_V2_FRAG_ENDLESS 0xff
2438 :
2439 : /* Repeat the time event endlessly (until removed) */
2440 : #define IWM_TE_V2_REPEAT_ENDLESS 0xff
2441 : /* If a Time Event has bounded repetitions, this is the maximal value */
2442 : #define IWM_TE_V2_REPEAT_MAX 0xfe
2443 :
2444 : #define IWM_TE_V2_PLACEMENT_POS 12
2445 : #define IWM_TE_V2_ABSENCE_POS 15
2446 :
2447 : /* Time event policy values (for time event cmd api v2)
2448 : * A notification (both event and fragment) includes a status indicating weather
2449 : * the FW was able to schedule the event or not. For fragment start/end
2450 : * notification the status is always success. There is no start/end fragment
2451 : * notification for monolithic events.
2452 : *
2453 : * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable
2454 : * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start
2455 : * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end
2456 : * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use
2457 : * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use.
2458 : * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2459 : * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2460 : * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
2461 : * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
2462 : * @IWM_TE_V2_DEP_OTHER: depends on another time event
2463 : * @IWM_TE_V2_DEP_TSF: depends on a specific time
2464 : * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC
2465 : * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event.
2466 : */
2467 : #define IWM_TE_V2_DEFAULT_POLICY 0x0
2468 :
2469 : /* notifications (event start/stop, fragment start/stop) */
2470 : #define IWM_TE_V2_NOTIF_HOST_EVENT_START (1 << 0)
2471 : #define IWM_TE_V2_NOTIF_HOST_EVENT_END (1 << 1)
2472 : #define IWM_TE_V2_NOTIF_INTERNAL_EVENT_START (1 << 2)
2473 : #define IWM_TE_V2_NOTIF_INTERNAL_EVENT_END (1 << 3)
2474 :
2475 : #define IWM_TE_V2_NOTIF_HOST_FRAG_START (1 << 4)
2476 : #define IWM_TE_V2_NOTIF_HOST_FRAG_END (1 << 5)
2477 : #define IWM_TE_V2_NOTIF_INTERNAL_FRAG_START (1 << 6)
2478 : #define IWM_TE_V2_NOTIF_INTERNAL_FRAG_END (1 << 7)
2479 : #define IWM_T2_V2_START_IMMEDIATELY (1 << 11)
2480 :
2481 : #define IWM_TE_V2_NOTIF_MSK 0xff
2482 :
2483 : /* placement characteristics */
2484 : #define IWM_TE_V2_DEP_OTHER (1 << IWM_TE_V2_PLACEMENT_POS)
2485 : #define IWM_TE_V2_DEP_TSF (1 << (IWM_TE_V2_PLACEMENT_POS + 1))
2486 : #define IWM_TE_V2_EVENT_SOCIOPATHIC (1 << (IWM_TE_V2_PLACEMENT_POS + 2))
2487 :
2488 : /* are we present or absent during the Time Event. */
2489 : #define IWM_TE_V2_ABSENCE (1 << IWM_TE_V2_ABSENCE_POS)
2490 :
2491 : /**
2492 : * struct iwm_time_event_cmd_api_v2 - configuring Time Events
2493 : * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
2494 : * with version 1. determined by IWM_UCODE_TLV_FLAGS)
2495 : * ( IWM_TIME_EVENT_CMD = 0x29 )
2496 : * @id_and_color: ID and color of the relevant MAC
2497 : * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2498 : * @id: this field has two meanings, depending on the action:
2499 : * If the action is ADD, then it means the type of event to add.
2500 : * For all other actions it is the unique event ID assigned when the
2501 : * event was added by the FW.
2502 : * @apply_time: When to start the Time Event (in GP2)
2503 : * @max_delay: maximum delay to event's start (apply time), in TU
2504 : * @depends_on: the unique ID of the event we depend on (if any)
2505 : * @interval: interval between repetitions, in TU
2506 : * @duration: duration of event in TU
2507 : * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2508 : * @max_frags: maximal number of fragments the Time Event can be divided to
2509 : * @policy: defines whether uCode shall notify the host or other uCode modules
2510 : * on event and/or fragment start and/or end
2511 : * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF
2512 : * IWM_TE_EVENT_SOCIOPATHIC
2513 : * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_*
2514 : */
2515 : struct iwm_time_event_cmd_v2 {
2516 : /* COMMON_INDEX_HDR_API_S_VER_1 */
2517 : uint32_t id_and_color;
2518 : uint32_t action;
2519 : uint32_t id;
2520 : /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */
2521 : uint32_t apply_time;
2522 : uint32_t max_delay;
2523 : uint32_t depends_on;
2524 : uint32_t interval;
2525 : uint32_t duration;
2526 : uint8_t repeat;
2527 : uint8_t max_frags;
2528 : uint16_t policy;
2529 : } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */
2530 :
2531 : /**
2532 : * struct iwm_time_event_resp - response structure to iwm_time_event_cmd
2533 : * @status: bit 0 indicates success, all others specify errors
2534 : * @id: the Time Event type
2535 : * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE
2536 : * @id_and_color: ID and color of the relevant MAC
2537 : */
2538 : struct iwm_time_event_resp {
2539 : uint32_t status;
2540 : uint32_t id;
2541 : uint32_t unique_id;
2542 : uint32_t id_and_color;
2543 : } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */
2544 :
2545 : /**
2546 : * struct iwm_time_event_notif - notifications of time event start/stop
2547 : * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a )
2548 : * @timestamp: action timestamp in GP2
2549 : * @session_id: session's unique id
2550 : * @unique_id: unique id of the Time Event itself
2551 : * @id_and_color: ID and color of the relevant MAC
2552 : * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END
2553 : * @status: true if scheduled, false otherwise (not executed)
2554 : */
2555 : struct iwm_time_event_notif {
2556 : uint32_t timestamp;
2557 : uint32_t session_id;
2558 : uint32_t unique_id;
2559 : uint32_t id_and_color;
2560 : uint32_t action;
2561 : uint32_t status;
2562 : } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */
2563 :
2564 :
2565 : /* Bindings and Time Quota */
2566 :
2567 : /**
2568 : * struct iwm_binding_cmd - configuring bindings
2569 : * ( IWM_BINDING_CONTEXT_CMD = 0x2b )
2570 : * @id_and_color: ID and color of the relevant Binding
2571 : * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2572 : * @macs: array of MAC id and colors which belong to the binding
2573 : * @phy: PHY id and color which belongs to the binding
2574 : */
2575 : struct iwm_binding_cmd {
2576 : /* COMMON_INDEX_HDR_API_S_VER_1 */
2577 : uint32_t id_and_color;
2578 : uint32_t action;
2579 : /* IWM_BINDING_DATA_API_S_VER_1 */
2580 : uint32_t macs[IWM_MAX_MACS_IN_BINDING];
2581 : uint32_t phy;
2582 : } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */
2583 :
2584 : /* The maximal number of fragments in the FW's schedule session */
2585 : #define IWM_MAX_QUOTA 128
2586 :
2587 : /**
2588 : * struct iwm_time_quota_data - configuration of time quota per binding
2589 : * @id_and_color: ID and color of the relevant Binding
2590 : * @quota: absolute time quota in TU. The scheduler will try to divide the
2591 : * remainig quota (after Time Events) according to this quota.
2592 : * @max_duration: max uninterrupted context duration in TU
2593 : */
2594 : struct iwm_time_quota_data {
2595 : uint32_t id_and_color;
2596 : uint32_t quota;
2597 : uint32_t max_duration;
2598 : } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */
2599 :
2600 : /**
2601 : * struct iwm_time_quota_cmd - configuration of time quota between bindings
2602 : * ( IWM_TIME_QUOTA_CMD = 0x2c )
2603 : * @quotas: allocations per binding
2604 : */
2605 : struct iwm_time_quota_cmd {
2606 : struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS];
2607 : } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
2608 :
2609 :
2610 : /* PHY context */
2611 :
2612 : /* Supported bands */
2613 : #define IWM_PHY_BAND_5 (0)
2614 : #define IWM_PHY_BAND_24 (1)
2615 :
2616 : /* Supported channel width, vary if there is VHT support */
2617 : #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0)
2618 : #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1)
2619 : #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2)
2620 : #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3)
2621 :
2622 : /*
2623 : * Control channel position:
2624 : * For legacy set bit means upper channel, otherwise lower.
2625 : * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
2626 : * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
2627 : * center_freq
2628 : * |
2629 : * 40Mhz |_______|_______|
2630 : * 80Mhz |_______|_______|_______|_______|
2631 : * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
2632 : * code 011 010 001 000 | 100 101 110 111
2633 : */
2634 : #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0)
2635 : #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1)
2636 : #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2)
2637 : #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3)
2638 : #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4)
2639 : #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5)
2640 : #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6)
2641 : #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7)
2642 :
2643 : /*
2644 : * @band: IWM_PHY_BAND_*
2645 : * @channel: channel number
2646 : * @width: PHY_[VHT|LEGACY]_CHANNEL_*
2647 : * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
2648 : */
2649 : struct iwm_fw_channel_info {
2650 : uint8_t band;
2651 : uint8_t channel;
2652 : uint8_t width;
2653 : uint8_t ctrl_pos;
2654 : } __packed;
2655 :
2656 : #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
2657 : #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \
2658 : (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS)
2659 : #define IWM_PHY_RX_CHAIN_VALID_POS (1)
2660 : #define IWM_PHY_RX_CHAIN_VALID_MSK \
2661 : (0x7 << IWM_PHY_RX_CHAIN_VALID_POS)
2662 : #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4)
2663 : #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \
2664 : (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS)
2665 : #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
2666 : #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
2667 : (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
2668 : #define IWM_PHY_RX_CHAIN_CNT_POS (10)
2669 : #define IWM_PHY_RX_CHAIN_CNT_MSK \
2670 : (0x3 << IWM_PHY_RX_CHAIN_CNT_POS)
2671 : #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12)
2672 : #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \
2673 : (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS)
2674 : #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14)
2675 : #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \
2676 : (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS)
2677 :
2678 : /* TODO: fix the value, make it depend on firmware at runtime? */
2679 : #define IWM_NUM_PHY_CTX 3
2680 :
2681 : /* TODO: complete missing documentation */
2682 : /**
2683 : * struct iwm_phy_context_cmd - config of the PHY context
2684 : * ( IWM_PHY_CONTEXT_CMD = 0x8 )
2685 : * @id_and_color: ID and color of the relevant Binding
2686 : * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2687 : * @apply_time: 0 means immediate apply and context switch.
2688 : * other value means apply new params after X usecs
2689 : * @tx_param_color: ???
2690 : * @channel_info:
2691 : * @txchain_info: ???
2692 : * @rxchain_info: ???
2693 : * @acquisition_data: ???
2694 : * @dsp_cfg_flags: set to 0
2695 : */
2696 : struct iwm_phy_context_cmd {
2697 : /* COMMON_INDEX_HDR_API_S_VER_1 */
2698 : uint32_t id_and_color;
2699 : uint32_t action;
2700 : /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */
2701 : uint32_t apply_time;
2702 : uint32_t tx_param_color;
2703 : struct iwm_fw_channel_info ci;
2704 : uint32_t txchain_info;
2705 : uint32_t rxchain_info;
2706 : uint32_t acquisition_data;
2707 : uint32_t dsp_cfg_flags;
2708 : } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */
2709 :
2710 : #define IWM_RX_INFO_PHY_CNT 8
2711 : #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1
2712 : #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
2713 : #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
2714 : #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
2715 : #define IWM_RX_INFO_ENERGY_ANT_A_POS 0
2716 : #define IWM_RX_INFO_ENERGY_ANT_B_POS 8
2717 : #define IWM_RX_INFO_ENERGY_ANT_C_POS 16
2718 :
2719 : #define IWM_RX_INFO_AGC_IDX 1
2720 : #define IWM_RX_INFO_RSSI_AB_IDX 2
2721 : #define IWM_OFDM_AGC_A_MSK 0x0000007f
2722 : #define IWM_OFDM_AGC_A_POS 0
2723 : #define IWM_OFDM_AGC_B_MSK 0x00003f80
2724 : #define IWM_OFDM_AGC_B_POS 7
2725 : #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000
2726 : #define IWM_OFDM_AGC_CODE_POS 20
2727 : #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff
2728 : #define IWM_OFDM_RSSI_A_POS 0
2729 : #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00
2730 : #define IWM_OFDM_RSSI_ALLBAND_A_POS 8
2731 : #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000
2732 : #define IWM_OFDM_RSSI_B_POS 16
2733 : #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
2734 : #define IWM_OFDM_RSSI_ALLBAND_B_POS 24
2735 :
2736 : /**
2737 : * struct iwm_rx_phy_info - phy info
2738 : * (IWM_REPLY_RX_PHY_CMD = 0xc0)
2739 : * @non_cfg_phy_cnt: non configurable DSP phy data byte count
2740 : * @cfg_phy_cnt: configurable DSP phy data byte count
2741 : * @stat_id: configurable DSP phy data set ID
2742 : * @reserved1:
2743 : * @system_timestamp: GP2 at on air rise
2744 : * @timestamp: TSF at on air rise
2745 : * @beacon_time_stamp: beacon at on-air rise
2746 : * @phy_flags: general phy flags: band, modulation, ...
2747 : * @channel: channel number
2748 : * @non_cfg_phy_buf: for various implementations of non_cfg_phy
2749 : * @rate_n_flags: IWM_RATE_MCS_*
2750 : * @byte_count: frame's byte-count
2751 : * @frame_time: frame's time on the air, based on byte count and frame rate
2752 : * calculation
2753 : * @mac_active_msk: what MACs were active when the frame was received
2754 : *
2755 : * Before each Rx, the device sends this data. It contains PHY information
2756 : * about the reception of the packet.
2757 : */
2758 : struct iwm_rx_phy_info {
2759 : uint8_t non_cfg_phy_cnt;
2760 : uint8_t cfg_phy_cnt;
2761 : uint8_t stat_id;
2762 : uint8_t reserved1;
2763 : uint32_t system_timestamp;
2764 : uint64_t timestamp;
2765 : uint32_t beacon_time_stamp;
2766 : uint16_t phy_flags;
2767 : #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2)
2768 : uint16_t channel;
2769 : uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT];
2770 : uint32_t rate_n_flags;
2771 : uint32_t byte_count;
2772 : uint16_t mac_active_msk;
2773 : uint16_t frame_time;
2774 : } __packed;
2775 :
2776 : struct iwm_rx_mpdu_res_start {
2777 : uint16_t byte_count;
2778 : uint16_t reserved;
2779 : } __packed;
2780 :
2781 : /**
2782 : * Values to parse %iwm_rx_phy_info phy_flags
2783 : * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
2784 : * @IWM_RX_RES_PHY_FLAGS_MOD_CCK:
2785 : * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
2786 : * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND:
2787 : * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
2788 : * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
2789 : * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
2790 : * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
2791 : * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
2792 : */
2793 : #define IWM_RX_RES_PHY_FLAGS_BAND_24 (1 << 0)
2794 : #define IWM_RX_RES_PHY_FLAGS_MOD_CCK (1 << 1)
2795 : #define IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE (1 << 2)
2796 : #define IWM_RX_RES_PHY_FLAGS_NARROW_BAND (1 << 3)
2797 : #define IWM_RX_RES_PHY_FLAGS_ANTENNA (0x7 << 4)
2798 : #define IWM_RX_RES_PHY_FLAGS_ANTENNA_POS 4
2799 : #define IWM_RX_RES_PHY_FLAGS_AGG (1 << 7)
2800 : #define IWM_RX_RES_PHY_FLAGS_OFDM_HT (1 << 8)
2801 : #define IWM_RX_RES_PHY_FLAGS_OFDM_GF (1 << 9)
2802 : #define IWM_RX_RES_PHY_FLAGS_OFDM_VHT (1 << 10)
2803 :
2804 : /**
2805 : * Values written by fw for each Rx packet
2806 : * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
2807 : * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
2808 : * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND:
2809 : * @IWM_RX_MPDU_RES_STATUS_KEY_VALID:
2810 : * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK:
2811 : * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
2812 : * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
2813 : * in the driver.
2814 : * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
2815 : * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
2816 : * alg = CCM only. Checks replay attack for 11w frames. Relevant only if
2817 : * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
2818 : * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
2819 : * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
2820 : * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
2821 : * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
2822 : * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
2823 : * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
2824 : * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
2825 : * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
2826 : * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
2827 : * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
2828 : * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
2829 : * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
2830 : * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
2831 : * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK:
2832 : * @IWM_RX_MPDU_RES_STATUS_RRF_KILL:
2833 : * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK:
2834 : * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK:
2835 : */
2836 : #define IWM_RX_MPDU_RES_STATUS_CRC_OK (1 << 0)
2837 : #define IWM_RX_MPDU_RES_STATUS_OVERRUN_OK (1 << 1)
2838 : #define IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND (1 << 2)
2839 : #define IWM_RX_MPDU_RES_STATUS_KEY_VALID (1 << 3)
2840 : #define IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK (1 << 4)
2841 : #define IWM_RX_MPDU_RES_STATUS_ICV_OK (1 << 5)
2842 : #define IWM_RX_MPDU_RES_STATUS_MIC_OK (1 << 6)
2843 : #define IWM_RX_MPDU_RES_STATUS_TTAK_OK (1 << 7)
2844 : #define IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR (1 << 7)
2845 : #define IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC (0 << 8)
2846 : #define IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC (1 << 8)
2847 : #define IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC (2 << 8)
2848 : #define IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC (3 << 8)
2849 : #define IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC (4 << 8)
2850 : #define IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC (6 << 8)
2851 : #define IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR (7 << 8)
2852 : #define IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK (7 << 8)
2853 : #define IWM_RX_MPDU_RES_STATUS_DEC_DONE (1 << 11)
2854 : #define IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP (1 << 12)
2855 : #define IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP (1 << 13)
2856 : #define IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT (1 << 14)
2857 : #define IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME (1 << 15)
2858 : #define IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK (0x3F0000)
2859 : #define IWM_RX_MPDU_RES_STATUS_STA_ID_MSK (0x1f000000)
2860 : #define IWM_RX_MPDU_RES_STATUS_RRF_KILL (1 << 29)
2861 : #define IWM_RX_MPDU_RES_STATUS_FILTERING_MSK (0xc00000)
2862 : #define IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK (0xc0000000)
2863 :
2864 : /**
2865 : * struct iwm_radio_version_notif - information on the radio version
2866 : * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 )
2867 : * @radio_flavor:
2868 : * @radio_step:
2869 : * @radio_dash:
2870 : */
2871 : struct iwm_radio_version_notif {
2872 : uint32_t radio_flavor;
2873 : uint32_t radio_step;
2874 : uint32_t radio_dash;
2875 : } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */
2876 :
2877 : #define IWM_CARD_ENABLED 0x00
2878 : #define IWM_HW_CARD_DISABLED 0x01
2879 : #define IWM_SW_CARD_DISABLED 0x02
2880 : #define IWM_CT_KILL_CARD_DISABLED 0x04
2881 : #define IWM_HALT_CARD_DISABLED 0x08
2882 : #define IWM_CARD_DISABLED_MSK 0x0f
2883 : #define IWM_CARD_IS_RX_ON 0x10
2884 :
2885 : /**
2886 : * struct iwm_radio_version_notif - information on the radio version
2887 : * (IWM_CARD_STATE_NOTIFICATION = 0xa1 )
2888 : * @flags: %iwm_card_state_flags
2889 : */
2890 : struct iwm_card_state_notif {
2891 : uint32_t flags;
2892 : } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */
2893 :
2894 : /**
2895 : * struct iwm_missed_beacons_notif - information on missed beacons
2896 : * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 )
2897 : * @mac_id: interface ID
2898 : * @consec_missed_beacons_since_last_rx: number of consecutive missed
2899 : * beacons since last RX.
2900 : * @consec_missed_beacons: number of consecutive missed beacons
2901 : * @num_expected_beacons:
2902 : * @num_recvd_beacons:
2903 : */
2904 : struct iwm_missed_beacons_notif {
2905 : uint32_t mac_id;
2906 : uint32_t consec_missed_beacons_since_last_rx;
2907 : uint32_t consec_missed_beacons;
2908 : uint32_t num_expected_beacons;
2909 : uint32_t num_recvd_beacons;
2910 : } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */
2911 :
2912 : /**
2913 : * struct iwm_mfuart_load_notif - mfuart image version & status
2914 : * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 )
2915 : * @installed_ver: installed image version
2916 : * @external_ver: external image version
2917 : * @status: MFUART loading status
2918 : * @duration: MFUART loading time
2919 : */
2920 : struct iwm_mfuart_load_notif {
2921 : uint32_t installed_ver;
2922 : uint32_t external_ver;
2923 : uint32_t status;
2924 : uint32_t duration;
2925 : } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/
2926 :
2927 : /**
2928 : * struct iwm_set_calib_default_cmd - set default value for calibration.
2929 : * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e )
2930 : * @calib_index: the calibration to set value for
2931 : * @length: of data
2932 : * @data: the value to set for the calibration result
2933 : */
2934 : struct iwm_set_calib_default_cmd {
2935 : uint16_t calib_index;
2936 : uint16_t length;
2937 : uint8_t data[0];
2938 : } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */
2939 :
2940 : #define IWM_MAX_PORT_ID_NUM 2
2941 : #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256
2942 :
2943 : /**
2944 : * struct iwm_mcast_filter_cmd - configure multicast filter.
2945 : * @filter_own: Set 1 to filter out multicast packets sent by station itself
2946 : * @port_id: Multicast MAC addresses array specifier. This is a strange way
2947 : * to identify network interface adopted in host-device IF.
2948 : * It is used by FW as index in array of addresses. This array has
2949 : * IWM_MAX_PORT_ID_NUM members.
2950 : * @count: Number of MAC addresses in the array
2951 : * @pass_all: Set 1 to pass all multicast packets.
2952 : * @bssid: current association BSSID.
2953 : * @addr_list: Place holder for array of MAC addresses.
2954 : * IMPORTANT: add padding if necessary to ensure DWORD alignment.
2955 : */
2956 : struct iwm_mcast_filter_cmd {
2957 : uint8_t filter_own;
2958 : uint8_t port_id;
2959 : uint8_t count;
2960 : uint8_t pass_all;
2961 : uint8_t bssid[6];
2962 : uint8_t reserved[2];
2963 : uint8_t addr_list[0];
2964 : } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */
2965 :
2966 : struct iwm_statistics_dbg {
2967 : uint32_t burst_check;
2968 : uint32_t burst_count;
2969 : uint32_t wait_for_silence_timeout_cnt;
2970 : uint32_t reserved[3];
2971 : } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */
2972 :
2973 : struct iwm_statistics_div {
2974 : uint32_t tx_on_a;
2975 : uint32_t tx_on_b;
2976 : uint32_t exec_time;
2977 : uint32_t probe_time;
2978 : uint32_t rssi_ant;
2979 : uint32_t reserved2;
2980 : } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */
2981 :
2982 : struct iwm_statistics_general_common {
2983 : uint32_t temperature; /* radio temperature */
2984 : uint32_t temperature_m; /* radio voltage */
2985 : struct iwm_statistics_dbg dbg;
2986 : uint32_t sleep_time;
2987 : uint32_t slots_out;
2988 : uint32_t slots_idle;
2989 : uint32_t ttl_timestamp;
2990 : struct iwm_statistics_div div;
2991 : uint32_t rx_enable_counter;
2992 : /*
2993 : * num_of_sos_states:
2994 : * count the number of times we have to re-tune
2995 : * in order to get out of bad PHY status
2996 : */
2997 : uint32_t num_of_sos_states;
2998 : } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
2999 :
3000 : struct iwm_statistics_rx_non_phy {
3001 : uint32_t bogus_cts; /* CTS received when not expecting CTS */
3002 : uint32_t bogus_ack; /* ACK received when not expecting ACK */
3003 : uint32_t non_bssid_frames; /* number of frames with BSSID that
3004 : * doesn't belong to the STA BSSID */
3005 : uint32_t filtered_frames; /* count frames that were dumped in the
3006 : * filtering process */
3007 : uint32_t non_channel_beacons; /* beacons with our bss id but not on
3008 : * our serving channel */
3009 : uint32_t channel_beacons; /* beacons with our bss id and in our
3010 : * serving channel */
3011 : uint32_t num_missed_bcon; /* number of missed beacons */
3012 : uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the
3013 : * ADC was in saturation */
3014 : uint32_t ina_detection_search_time;/* total time (in 0.8us) searched
3015 : * for INA */
3016 : uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */
3017 : uint32_t interference_data_flag; /* flag for interference data
3018 : * availability. 1 when data is
3019 : * available. */
3020 : uint32_t channel_load; /* counts RX Enable time in uSec */
3021 : uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM
3022 : * and CCK) counter */
3023 : uint32_t beacon_rssi_a;
3024 : uint32_t beacon_rssi_b;
3025 : uint32_t beacon_rssi_c;
3026 : uint32_t beacon_energy_a;
3027 : uint32_t beacon_energy_b;
3028 : uint32_t beacon_energy_c;
3029 : uint32_t num_bt_kills;
3030 : uint32_t mac_id;
3031 : uint32_t directed_data_mpdu;
3032 : } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */
3033 :
3034 : struct iwm_statistics_rx_phy {
3035 : uint32_t ina_cnt;
3036 : uint32_t fina_cnt;
3037 : uint32_t plcp_err;
3038 : uint32_t crc32_err;
3039 : uint32_t overrun_err;
3040 : uint32_t early_overrun_err;
3041 : uint32_t crc32_good;
3042 : uint32_t false_alarm_cnt;
3043 : uint32_t fina_sync_err_cnt;
3044 : uint32_t sfd_timeout;
3045 : uint32_t fina_timeout;
3046 : uint32_t unresponded_rts;
3047 : uint32_t rxe_frame_limit_overrun;
3048 : uint32_t sent_ack_cnt;
3049 : uint32_t sent_cts_cnt;
3050 : uint32_t sent_ba_rsp_cnt;
3051 : uint32_t dsp_self_kill;
3052 : uint32_t mh_format_err;
3053 : uint32_t re_acq_main_rssi_sum;
3054 : uint32_t reserved;
3055 : } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */
3056 :
3057 : struct iwm_statistics_rx_ht_phy {
3058 : uint32_t plcp_err;
3059 : uint32_t overrun_err;
3060 : uint32_t early_overrun_err;
3061 : uint32_t crc32_good;
3062 : uint32_t crc32_err;
3063 : uint32_t mh_format_err;
3064 : uint32_t agg_crc32_good;
3065 : uint32_t agg_mpdu_cnt;
3066 : uint32_t agg_cnt;
3067 : uint32_t unsupport_mcs;
3068 : } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */
3069 :
3070 : #define IWM_MAX_CHAINS 3
3071 :
3072 : struct iwm_statistics_tx_non_phy_agg {
3073 : uint32_t ba_timeout;
3074 : uint32_t ba_reschedule_frames;
3075 : uint32_t scd_query_agg_frame_cnt;
3076 : uint32_t scd_query_no_agg;
3077 : uint32_t scd_query_agg;
3078 : uint32_t scd_query_mismatch;
3079 : uint32_t frame_not_ready;
3080 : uint32_t underrun;
3081 : uint32_t bt_prio_kill;
3082 : uint32_t rx_ba_rsp_cnt;
3083 : int8_t txpower[IWM_MAX_CHAINS];
3084 : int8_t reserved;
3085 : uint32_t reserved2;
3086 : } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */
3087 :
3088 : struct iwm_statistics_tx_channel_width {
3089 : uint32_t ext_cca_narrow_ch20[1];
3090 : uint32_t ext_cca_narrow_ch40[2];
3091 : uint32_t ext_cca_narrow_ch80[3];
3092 : uint32_t ext_cca_narrow_ch160[4];
3093 : uint32_t last_tx_ch_width_indx;
3094 : uint32_t rx_detected_per_ch_width[4];
3095 : uint32_t success_per_ch_width[4];
3096 : uint32_t fail_per_ch_width[4];
3097 : }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */
3098 :
3099 : struct iwm_statistics_tx {
3100 : uint32_t preamble_cnt;
3101 : uint32_t rx_detected_cnt;
3102 : uint32_t bt_prio_defer_cnt;
3103 : uint32_t bt_prio_kill_cnt;
3104 : uint32_t few_bytes_cnt;
3105 : uint32_t cts_timeout;
3106 : uint32_t ack_timeout;
3107 : uint32_t expected_ack_cnt;
3108 : uint32_t actual_ack_cnt;
3109 : uint32_t dump_msdu_cnt;
3110 : uint32_t burst_abort_next_frame_mismatch_cnt;
3111 : uint32_t burst_abort_missing_next_frame_cnt;
3112 : uint32_t cts_timeout_collision;
3113 : uint32_t ack_or_ba_timeout_collision;
3114 : struct iwm_statistics_tx_non_phy_agg agg;
3115 : struct iwm_statistics_tx_channel_width channel_width;
3116 : } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */
3117 :
3118 :
3119 : struct iwm_statistics_bt_activity {
3120 : uint32_t hi_priority_tx_req_cnt;
3121 : uint32_t hi_priority_tx_denied_cnt;
3122 : uint32_t lo_priority_tx_req_cnt;
3123 : uint32_t lo_priority_tx_denied_cnt;
3124 : uint32_t hi_priority_rx_req_cnt;
3125 : uint32_t hi_priority_rx_denied_cnt;
3126 : uint32_t lo_priority_rx_req_cnt;
3127 : uint32_t lo_priority_rx_denied_cnt;
3128 : } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */
3129 :
3130 : struct iwm_statistics_general {
3131 : struct iwm_statistics_general_common common;
3132 : uint32_t beacon_filtered;
3133 : uint32_t missed_beacons;
3134 : int8_t beacon_filter_average_energy;
3135 : int8_t beacon_filter_reason;
3136 : int8_t beacon_filter_current_energy;
3137 : int8_t beacon_filter_reserved;
3138 : uint32_t beacon_filter_delta_time;
3139 : struct iwm_statistics_bt_activity bt_activity;
3140 : } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
3141 :
3142 : struct iwm_statistics_rx {
3143 : struct iwm_statistics_rx_phy ofdm;
3144 : struct iwm_statistics_rx_phy cck;
3145 : struct iwm_statistics_rx_non_phy general;
3146 : struct iwm_statistics_rx_ht_phy ofdm_ht;
3147 : } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */
3148 :
3149 : /*
3150 : * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
3151 : *
3152 : * By default, uCode issues this notification after receiving a beacon
3153 : * while associated. To disable this behavior, set DISABLE_NOTIF flag in the
3154 : * IWM_REPLY_STATISTICS_CMD 0x9c, above.
3155 : *
3156 : * Statistics counters continue to increment beacon after beacon, but are
3157 : * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD
3158 : * 0x9c with CLEAR_STATS bit set (see above).
3159 : *
3160 : * uCode also issues this notification during scans. uCode clears statistics
3161 : * appropriately so that each notification contains statistics for only the
3162 : * one channel that has just been scanned.
3163 : */
3164 :
3165 : struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */
3166 : uint32_t flag;
3167 : struct iwm_statistics_rx rx;
3168 : struct iwm_statistics_tx tx;
3169 : struct iwm_statistics_general general;
3170 : } __packed;
3171 :
3172 : /***********************************
3173 : * Smart Fifo API
3174 : ***********************************/
3175 : /* Smart Fifo state */
3176 : #define IWM_SF_LONG_DELAY_ON 0 /* should never be called by driver */
3177 : #define IWM_SF_FULL_ON 1
3178 : #define IWM_SF_UNINIT 2
3179 : #define IWM_SF_INIT_OFF 3
3180 : #define IWM_SF_HW_NUM_STATES 4
3181 :
3182 : /* Smart Fifo possible scenario */
3183 : #define IWM_SF_SCENARIO_SINGLE_UNICAST 0
3184 : #define IWM_SF_SCENARIO_AGG_UNICAST 1
3185 : #define IWM_SF_SCENARIO_MULTICAST 2
3186 : #define IWM_SF_SCENARIO_BA_RESP 3
3187 : #define IWM_SF_SCENARIO_TX_RESP 4
3188 : #define IWM_SF_NUM_SCENARIO 5
3189 :
3190 : #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */
3191 : #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */
3192 :
3193 : /* smart FIFO default values */
3194 : #define IWM_SF_W_MARK_SISO 4096
3195 : #define IWM_SF_W_MARK_MIMO2 8192
3196 : #define IWM_SF_W_MARK_MIMO3 6144
3197 : #define IWM_SF_W_MARK_LEGACY 4096
3198 : #define IWM_SF_W_MARK_SCAN 4096
3199 :
3200 : /* SF Scenarios timers for default configuration (aligned to 32 uSec) */
3201 : #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3202 : #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3203 : #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3204 : #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3205 : #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */
3206 : #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3207 : #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */
3208 : #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */
3209 : #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */
3210 : #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */
3211 :
3212 : /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */
3213 : #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */
3214 : #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */
3215 : #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */
3216 : #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */
3217 : #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */
3218 : #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */
3219 : #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */
3220 : #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */
3221 : #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */
3222 : #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
3223 :
3224 : #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
3225 :
3226 : #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16)
3227 :
3228 : /**
3229 : * Smart Fifo configuration command.
3230 : * @state: smart fifo state, types listed in enum %iwm_sf_state.
3231 : * @watermark: Minimum allowed availabe free space in RXF for transient state.
3232 : * @long_delay_timeouts: aging and idle timer values for each scenario
3233 : * in long delay state.
3234 : * @full_on_timeouts: timer values for each scenario in full on state.
3235 : */
3236 : struct iwm_sf_cfg_cmd {
3237 : uint32_t state;
3238 : uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER];
3239 : uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3240 : uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3241 : } __packed; /* IWM_SF_CFG_API_S_VER_2 */
3242 :
3243 : /*
3244 : * The first MAC indices (starting from 0)
3245 : * are available to the driver, AUX follows
3246 : */
3247 : #define IWM_MAC_INDEX_AUX 4
3248 : #define IWM_MAC_INDEX_MIN_DRIVER 0
3249 : #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX
3250 :
3251 : #define IWM_AC_BK 0
3252 : #define IWM_AC_BE 1
3253 : #define IWM_AC_VI 2
3254 : #define IWM_AC_VO 3
3255 : #define IWM_AC_NUM 4
3256 :
3257 : /**
3258 : * MAC context flags
3259 : * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames,
3260 : * this will require CCK RTS/CTS2self.
3261 : * RTS/CTS will protect full burst time.
3262 : * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection
3263 : * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
3264 : * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self
3265 : */
3266 : #define IWM_MAC_PROT_FLG_TGG_PROTECT (1 << 3)
3267 : #define IWM_MAC_PROT_FLG_HT_PROT (1 << 23)
3268 : #define IWM_MAC_PROT_FLG_FAT_PROT (1 << 24)
3269 : #define IWM_MAC_PROT_FLG_SELF_CTS_EN (1 << 30)
3270 :
3271 : #define IWM_MAC_FLG_SHORT_SLOT (1 << 4)
3272 : #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5)
3273 :
3274 : /**
3275 : * Supported MAC types
3276 : * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type
3277 : * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal)
3278 : * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?)
3279 : * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS
3280 : * @IWM_FW_MAC_TYPE_IBSS: IBSS
3281 : * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station
3282 : * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device
3283 : * @IWM_FW_MAC_TYPE_P2P_STA: P2P client
3284 : * @IWM_FW_MAC_TYPE_GO: P2P GO
3285 : * @IWM_FW_MAC_TYPE_TEST: ?
3286 : * @IWM_FW_MAC_TYPE_MAX: highest support MAC type
3287 : */
3288 : #define IWM_FW_MAC_TYPE_FIRST 1
3289 : #define IWM_FW_MAC_TYPE_AUX IWM_FW_MAC_TYPE_FIRST
3290 : #define IWM_FW_MAC_TYPE_LISTENER 2
3291 : #define IWM_FW_MAC_TYPE_PIBSS 3
3292 : #define IWM_FW_MAC_TYPE_IBSS 4
3293 : #define IWM_FW_MAC_TYPE_BSS_STA 5
3294 : #define IWM_FW_MAC_TYPE_P2P_DEVICE 6
3295 : #define IWM_FW_MAC_TYPE_P2P_STA 7
3296 : #define IWM_FW_MAC_TYPE_GO 8
3297 : #define IWM_FW_MAC_TYPE_TEST 9
3298 : #define IWM_FW_MAC_TYPE_MAX IWM_FW_MAC_TYPE_TEST
3299 : /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */
3300 :
3301 : /**
3302 : * TSF hw timer ID
3303 : * @IWM_TSF_ID_A: use TSF A
3304 : * @IWM_TSF_ID_B: use TSF B
3305 : * @IWM_TSF_ID_C: use TSF C
3306 : * @IWM_TSF_ID_D: use TSF D
3307 : * @IWM_NUM_TSF_IDS: number of TSF timers available
3308 : */
3309 : #define IWM_TSF_ID_A 0
3310 : #define IWM_TSF_ID_B 1
3311 : #define IWM_TSF_ID_C 2
3312 : #define IWM_TSF_ID_D 3
3313 : #define IWM_NUM_TSF_IDS 4
3314 : /* IWM_TSF_ID_API_E_VER_1 */
3315 :
3316 : /**
3317 : * struct iwm_mac_data_ap - configuration data for AP MAC context
3318 : * @beacon_time: beacon transmit time in system time
3319 : * @beacon_tsf: beacon transmit time in TSF
3320 : * @bi: beacon interval in TU
3321 : * @bi_reciprocal: 2^32 / bi
3322 : * @dtim_interval: dtim transmit time in TU
3323 : * @dtim_reciprocal: 2^32 / dtim_interval
3324 : * @mcast_qid: queue ID for multicast traffic
3325 : * @beacon_template: beacon template ID
3326 : */
3327 : struct iwm_mac_data_ap {
3328 : uint32_t beacon_time;
3329 : uint64_t beacon_tsf;
3330 : uint32_t bi;
3331 : uint32_t bi_reciprocal;
3332 : uint32_t dtim_interval;
3333 : uint32_t dtim_reciprocal;
3334 : uint32_t mcast_qid;
3335 : uint32_t beacon_template;
3336 : } __packed; /* AP_MAC_DATA_API_S_VER_1 */
3337 :
3338 : /**
3339 : * struct iwm_mac_data_ibss - configuration data for IBSS MAC context
3340 : * @beacon_time: beacon transmit time in system time
3341 : * @beacon_tsf: beacon transmit time in TSF
3342 : * @bi: beacon interval in TU
3343 : * @bi_reciprocal: 2^32 / bi
3344 : * @beacon_template: beacon template ID
3345 : */
3346 : struct iwm_mac_data_ibss {
3347 : uint32_t beacon_time;
3348 : uint64_t beacon_tsf;
3349 : uint32_t bi;
3350 : uint32_t bi_reciprocal;
3351 : uint32_t beacon_template;
3352 : } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */
3353 :
3354 : /**
3355 : * struct iwm_mac_data_sta - configuration data for station MAC context
3356 : * @is_assoc: 1 for associated state, 0 otherwise
3357 : * @dtim_time: DTIM arrival time in system time
3358 : * @dtim_tsf: DTIM arrival time in TSF
3359 : * @bi: beacon interval in TU, applicable only when associated
3360 : * @bi_reciprocal: 2^32 / bi , applicable only when associated
3361 : * @dtim_interval: DTIM interval in TU, applicable only when associated
3362 : * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated
3363 : * @listen_interval: in beacon intervals, applicable only when associated
3364 : * @assoc_id: unique ID assigned by the AP during association
3365 : */
3366 : struct iwm_mac_data_sta {
3367 : uint32_t is_assoc;
3368 : uint32_t dtim_time;
3369 : uint64_t dtim_tsf;
3370 : uint32_t bi;
3371 : uint32_t bi_reciprocal;
3372 : uint32_t dtim_interval;
3373 : uint32_t dtim_reciprocal;
3374 : uint32_t listen_interval;
3375 : uint32_t assoc_id;
3376 : uint32_t assoc_beacon_arrive_time;
3377 : } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */
3378 :
3379 : /**
3380 : * struct iwm_mac_data_go - configuration data for P2P GO MAC context
3381 : * @ap: iwm_mac_data_ap struct with most config data
3382 : * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3383 : * 0 indicates that there is no CT window.
3384 : * @opp_ps_enabled: indicate that opportunistic PS allowed
3385 : */
3386 : struct iwm_mac_data_go {
3387 : struct iwm_mac_data_ap ap;
3388 : uint32_t ctwin;
3389 : uint32_t opp_ps_enabled;
3390 : } __packed; /* GO_MAC_DATA_API_S_VER_1 */
3391 :
3392 : /**
3393 : * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context
3394 : * @sta: iwm_mac_data_sta struct with most config data
3395 : * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3396 : * 0 indicates that there is no CT window.
3397 : */
3398 : struct iwm_mac_data_p2p_sta {
3399 : struct iwm_mac_data_sta sta;
3400 : uint32_t ctwin;
3401 : } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */
3402 :
3403 : /**
3404 : * struct iwm_mac_data_pibss - Pseudo IBSS config data
3405 : * @stats_interval: interval in TU between statistics notifications to host.
3406 : */
3407 : struct iwm_mac_data_pibss {
3408 : uint32_t stats_interval;
3409 : } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */
3410 :
3411 : /*
3412 : * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC
3413 : * context.
3414 : * @is_disc_extended: if set to true, P2P Device discoverability is enabled on
3415 : * other channels as well. This should be to true only in case that the
3416 : * device is discoverable and there is an active GO. Note that setting this
3417 : * field when not needed, will increase the number of interrupts and have
3418 : * effect on the platform power, as this setting opens the Rx filters on
3419 : * all macs.
3420 : */
3421 : struct iwm_mac_data_p2p_dev {
3422 : uint32_t is_disc_extended;
3423 : } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */
3424 :
3425 : /**
3426 : * MAC context filter flags
3427 : * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames
3428 : * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and
3429 : * control frames to the host
3430 : * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames
3431 : * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames
3432 : * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames
3433 : * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host
3434 : * (in station mode when associated)
3435 : * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames
3436 : * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames
3437 : * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host
3438 : */
3439 : #define IWM_MAC_FILTER_IN_PROMISC (1 << 0)
3440 : #define IWM_MAC_FILTER_IN_CONTROL_AND_MGMT (1 << 1)
3441 : #define IWM_MAC_FILTER_ACCEPT_GRP (1 << 2)
3442 : #define IWM_MAC_FILTER_DIS_DECRYPT (1 << 3)
3443 : #define IWM_MAC_FILTER_DIS_GRP_DECRYPT (1 << 4)
3444 : #define IWM_MAC_FILTER_IN_BEACON (1 << 6)
3445 : #define IWM_MAC_FILTER_OUT_BCAST (1 << 8)
3446 : #define IWM_MAC_FILTER_IN_CRC32 (1 << 11)
3447 : #define IWM_MAC_FILTER_IN_PROBE_REQUEST (1 << 12)
3448 :
3449 : /**
3450 : * QoS flags
3451 : * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ?
3452 : * @IWM_MAC_QOS_FLG_TGN: HT is enabled
3453 : * @IWM_MAC_QOS_FLG_TXOP_TYPE: ?
3454 : *
3455 : */
3456 : #define IWM_MAC_QOS_FLG_UPDATE_EDCA (1 << 0)
3457 : #define IWM_MAC_QOS_FLG_TGN (1 << 1)
3458 : #define IWM_MAC_QOS_FLG_TXOP_TYPE (1 << 4)
3459 :
3460 : /**
3461 : * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD
3462 : * @cw_min: Contention window, start value in numbers of slots.
3463 : * Should be a power-of-2, minus 1. Device's default is 0x0f.
3464 : * @cw_max: Contention window, max value in numbers of slots.
3465 : * Should be a power-of-2, minus 1. Device's default is 0x3f.
3466 : * @aifsn: Number of slots in Arbitration Interframe Space (before
3467 : * performing random backoff timing prior to Tx). Device default 1.
3468 : * @fifos_mask: FIFOs used by this MAC for this AC
3469 : * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0.
3470 : *
3471 : * One instance of this config struct for each of 4 EDCA access categories
3472 : * in struct iwm_qosparam_cmd.
3473 : *
3474 : * Device will automatically increase contention window by (2*CW) + 1 for each
3475 : * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW
3476 : * value, to cap the CW value.
3477 : */
3478 : struct iwm_ac_qos {
3479 : uint16_t cw_min;
3480 : uint16_t cw_max;
3481 : uint8_t aifsn;
3482 : uint8_t fifos_mask;
3483 : uint16_t edca_txop;
3484 : } __packed; /* IWM_AC_QOS_API_S_VER_2 */
3485 :
3486 : /**
3487 : * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts
3488 : * ( IWM_MAC_CONTEXT_CMD = 0x28 )
3489 : * @id_and_color: ID and color of the MAC
3490 : * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
3491 : * @mac_type: one of IWM_FW_MAC_TYPE_*
3492 : * @tsf_id: TSF HW timer, one of IWM_TSF_ID_*
3493 : * @node_addr: MAC address
3494 : * @bssid_addr: BSSID
3495 : * @cck_rates: basic rates available for CCK
3496 : * @ofdm_rates: basic rates available for OFDM
3497 : * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_*
3498 : * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise
3499 : * @short_slot: 0x10 for enabling short slots, 0 otherwise
3500 : * @filter_flags: combination of IWM_MAC_FILTER_*
3501 : * @qos_flags: from IWM_MAC_QOS_FLG_*
3502 : * @ac: one iwm_mac_qos configuration for each AC
3503 : * @mac_specific: one of struct iwm_mac_data_*, according to mac_type
3504 : */
3505 : struct iwm_mac_ctx_cmd {
3506 : /* COMMON_INDEX_HDR_API_S_VER_1 */
3507 : uint32_t id_and_color;
3508 : uint32_t action;
3509 : /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */
3510 : uint32_t mac_type;
3511 : uint32_t tsf_id;
3512 : uint8_t node_addr[6];
3513 : uint16_t reserved_for_node_addr;
3514 : uint8_t bssid_addr[6];
3515 : uint16_t reserved_for_bssid_addr;
3516 : uint32_t cck_rates;
3517 : uint32_t ofdm_rates;
3518 : uint32_t protection_flags;
3519 : uint32_t cck_short_preamble;
3520 : uint32_t short_slot;
3521 : uint32_t filter_flags;
3522 : /* IWM_MAC_QOS_PARAM_API_S_VER_1 */
3523 : uint32_t qos_flags;
3524 : struct iwm_ac_qos ac[IWM_AC_NUM+1];
3525 : /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */
3526 : union {
3527 : struct iwm_mac_data_ap ap;
3528 : struct iwm_mac_data_go go;
3529 : struct iwm_mac_data_sta sta;
3530 : struct iwm_mac_data_p2p_sta p2p_sta;
3531 : struct iwm_mac_data_p2p_dev p2p_dev;
3532 : struct iwm_mac_data_pibss pibss;
3533 : struct iwm_mac_data_ibss ibss;
3534 : };
3535 : } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */
3536 :
3537 0 : static inline uint32_t iwm_reciprocal(uint32_t v)
3538 : {
3539 0 : if (!v)
3540 0 : return 0;
3541 0 : return 0xFFFFFFFF / v;
3542 0 : }
3543 :
3544 : #define IWM_NONQOS_SEQ_GET 0x1
3545 : #define IWM_NONQOS_SEQ_SET 0x2
3546 : struct iwm_nonqos_seq_query_cmd {
3547 : uint32_t get_set_flag;
3548 : uint32_t mac_id_n_color;
3549 : uint16_t value;
3550 : uint16_t reserved;
3551 : } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */
3552 :
3553 : /* Power Management Commands, Responses, Notifications */
3554 :
3555 : /* Radio LP RX Energy Threshold measured in dBm */
3556 : #define IWM_POWER_LPRX_RSSI_THRESHOLD 75
3557 : #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94
3558 : #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30
3559 :
3560 : /**
3561 : * Masks for iwm_mac_power_cmd command flags
3562 : * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3563 : * receiver and transmitter. '0' - does not allow.
3564 : * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management,
3565 : * '1' Driver enables PM (use rest of parameters)
3566 : * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM,
3567 : * '1' PM could sleep over DTIM till listen Interval.
3568 : * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all
3569 : * access categories are both delivery and trigger enabled.
3570 : * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and
3571 : * PBW Snoozing enabled
3572 : * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask
3573 : * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable.
3574 : * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving
3575 : * detection enablement
3576 : */
3577 : #define IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0)
3578 : #define IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK (1 << 1)
3579 : #define IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK (1 << 2)
3580 : #define IWM_POWER_FLAGS_SNOOZE_ENA_MSK (1 << 5)
3581 : #define IWM_POWER_FLAGS_BT_SCO_ENA (1 << 8)
3582 : #define IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK (1 << 9)
3583 : #define IWM_POWER_FLAGS_LPRX_ENA_MSK (1 << 11)
3584 : #define IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK (1 << 12)
3585 :
3586 : #define IWM_POWER_VEC_SIZE 5
3587 :
3588 : /**
3589 : * Masks for device power command flags
3590 : * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK:
3591 : * '1' Allow to save power by turning off receiver and transmitter.
3592 : * '0' Do not allow. This flag should be always set to '1' unless
3593 : * one needs to disable actual power down for debug purposes.
3594 : * @IWM_DEVICE_POWER_FLAGS_CAM_MSK:
3595 : * '1' CAM (Continuous Active Mode) is set, power management is disabled.
3596 : * '0' Power management is enabled, one of the power schemes is applied.
3597 : */
3598 : #define IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0)
3599 : #define IWM_DEVICE_POWER_FLAGS_CAM_MSK (1 << 13)
3600 :
3601 : /**
3602 : * struct iwm_device_power_cmd - device wide power command.
3603 : * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response)
3604 : *
3605 : * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_*
3606 : */
3607 : struct iwm_device_power_cmd {
3608 : /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3609 : uint16_t flags;
3610 : uint16_t reserved;
3611 : } __packed;
3612 :
3613 : /**
3614 : * struct iwm_mac_power_cmd - New power command containing uAPSD support
3615 : * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response)
3616 : * @id_and_color: MAC contex identifier
3617 : * @flags: Power table command flags from POWER_FLAGS_*
3618 : * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3619 : * Minimum allowed:- 3 * DTIM. Keep alive period must be
3620 : * set regardless of power scheme or current power state.
3621 : * FW use this value also when PM is disabled.
3622 : * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3623 : * PSM transition - legacy PM
3624 : * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3625 : * PSM transition - legacy PM
3626 : * @sleep_interval: not in use
3627 : * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3628 : * is set. For example, if it is required to skip over
3629 : * one DTIM, this value need to be set to 2 (DTIM periods).
3630 : * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to
3631 : * PSM transition - uAPSD
3632 : * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to
3633 : * PSM transition - uAPSD
3634 : * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3635 : * Default: 80dbm
3636 : * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set
3637 : * @snooze_interval: Maximum time between attempts to retrieve buffered data
3638 : * from the AP [msec]
3639 : * @snooze_window: A window of time in which PBW snoozing insures that all
3640 : * packets received. It is also the minimum time from last
3641 : * received unicast RX packet, before client stops snoozing
3642 : * for data. [msec]
3643 : * @snooze_step: TBD
3644 : * @qndp_tid: TID client shall use for uAPSD QNDP triggers
3645 : * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for
3646 : * each corresponding AC.
3647 : * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values.
3648 : * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct
3649 : * values.
3650 : * @heavy_tx_thld_packets: TX threshold measured in number of packets
3651 : * @heavy_rx_thld_packets: RX threshold measured in number of packets
3652 : * @heavy_tx_thld_percentage: TX threshold measured in load's percentage
3653 : * @heavy_rx_thld_percentage: RX threshold measured in load's percentage
3654 : * @limited_ps_threshold:
3655 : */
3656 : struct iwm_mac_power_cmd {
3657 : /* CONTEXT_DESC_API_T_VER_1 */
3658 : uint32_t id_and_color;
3659 :
3660 : /* CLIENT_PM_POWER_TABLE_S_VER_1 */
3661 : uint16_t flags;
3662 : uint16_t keep_alive_seconds;
3663 : uint32_t rx_data_timeout;
3664 : uint32_t tx_data_timeout;
3665 : uint32_t rx_data_timeout_uapsd;
3666 : uint32_t tx_data_timeout_uapsd;
3667 : uint8_t lprx_rssi_threshold;
3668 : uint8_t skip_dtim_periods;
3669 : uint16_t snooze_interval;
3670 : uint16_t snooze_window;
3671 : uint8_t snooze_step;
3672 : uint8_t qndp_tid;
3673 : uint8_t uapsd_ac_flags;
3674 : uint8_t uapsd_max_sp;
3675 : uint8_t heavy_tx_thld_packets;
3676 : uint8_t heavy_rx_thld_packets;
3677 : uint8_t heavy_tx_thld_percentage;
3678 : uint8_t heavy_rx_thld_percentage;
3679 : uint8_t limited_ps_threshold;
3680 : uint8_t reserved;
3681 : } __packed;
3682 :
3683 : #define IWM_DEFAULT_PS_TX_DATA_TIMEOUT (100 * 1000)
3684 : #define IWM_DEFAULT_PS_RX_DATA_TIMEOUT (100 * 1000)
3685 :
3686 : /*
3687 : * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when
3688 : * associated AP is identified as improperly implementing uAPSD protocol.
3689 : * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78
3690 : * @sta_id: index of station in uCode's station table - associated AP ID in
3691 : * this context.
3692 : */
3693 : struct iwm_uapsd_misbehaving_ap_notif {
3694 : uint32_t sta_id;
3695 : uint8_t mac_id;
3696 : uint8_t reserved[3];
3697 : } __packed;
3698 :
3699 : /**
3700 : * struct iwm_beacon_filter_cmd
3701 : * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command)
3702 : * @id_and_color: MAC contex identifier
3703 : * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon
3704 : * to driver if delta in Energy values calculated for this and last
3705 : * passed beacon is greater than this threshold. Zero value means that
3706 : * the Energy change is ignored for beacon filtering, and beacon will
3707 : * not be forced to be sent to driver regardless of this delta. Typical
3708 : * energy delta 5dB.
3709 : * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state.
3710 : * Send beacon to driver if delta in Energy values calculated for this
3711 : * and last passed beacon is greater than this threshold. Zero value
3712 : * means that the Energy change is ignored for beacon filtering while in
3713 : * Roaming state, typical energy delta 1dB.
3714 : * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values
3715 : * calculated for current beacon is less than the threshold, use
3716 : * Roaming Energy Delta Threshold, otherwise use normal Energy Delta
3717 : * Threshold. Typical energy threshold is -72dBm.
3718 : * @bf_temp_threshold: This threshold determines the type of temperature
3719 : * filtering (Slow or Fast) that is selected (Units are in Celsuis):
3720 : * If the current temperature is above this threshold - Fast filter
3721 : * will be used, If the current temperature is below this threshold -
3722 : * Slow filter will be used.
3723 : * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values
3724 : * calculated for this and the last passed beacon is greater than this
3725 : * threshold. Zero value means that the temperature change is ignored for
3726 : * beacon filtering; beacons will not be forced to be sent to driver
3727 : * regardless of whether its temerature has been changed.
3728 : * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values
3729 : * calculated for this and the last passed beacon is greater than this
3730 : * threshold. Zero value means that the temperature change is ignored for
3731 : * beacon filtering; beacons will not be forced to be sent to driver
3732 : * regardless of whether its temerature has been changed.
3733 : * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled.
3734 : * @bf_escape_timer: Send beacons to driver if no beacons were passed
3735 : * for a specific period of time. Units: Beacons.
3736 : * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed
3737 : * for a longer period of time then this escape-timeout. Units: Beacons.
3738 : * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled.
3739 : */
3740 : struct iwm_beacon_filter_cmd {
3741 : uint32_t bf_energy_delta;
3742 : uint32_t bf_roaming_energy_delta;
3743 : uint32_t bf_roaming_state;
3744 : uint32_t bf_temp_threshold;
3745 : uint32_t bf_temp_fast_filter;
3746 : uint32_t bf_temp_slow_filter;
3747 : uint32_t bf_enable_beacon_filter;
3748 : uint32_t bf_debug_flag;
3749 : uint32_t bf_escape_timer;
3750 : uint32_t ba_escape_timer;
3751 : uint32_t ba_enable_beacon_abort;
3752 : } __packed;
3753 :
3754 : /* Beacon filtering and beacon abort */
3755 : #define IWM_BF_ENERGY_DELTA_DEFAULT 5
3756 : #define IWM_BF_ENERGY_DELTA_MAX 255
3757 : #define IWM_BF_ENERGY_DELTA_MIN 0
3758 :
3759 : #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1
3760 : #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255
3761 : #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0
3762 :
3763 : #define IWM_BF_ROAMING_STATE_DEFAULT 72
3764 : #define IWM_BF_ROAMING_STATE_MAX 255
3765 : #define IWM_BF_ROAMING_STATE_MIN 0
3766 :
3767 : #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112
3768 : #define IWM_BF_TEMP_THRESHOLD_MAX 255
3769 : #define IWM_BF_TEMP_THRESHOLD_MIN 0
3770 :
3771 : #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1
3772 : #define IWM_BF_TEMP_FAST_FILTER_MAX 255
3773 : #define IWM_BF_TEMP_FAST_FILTER_MIN 0
3774 :
3775 : #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5
3776 : #define IWM_BF_TEMP_SLOW_FILTER_MAX 255
3777 : #define IWM_BF_TEMP_SLOW_FILTER_MIN 0
3778 :
3779 : #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1
3780 :
3781 : #define IWM_BF_DEBUG_FLAG_DEFAULT 0
3782 :
3783 : #define IWM_BF_ESCAPE_TIMER_DEFAULT 50
3784 : #define IWM_BF_ESCAPE_TIMER_MAX 1024
3785 : #define IWM_BF_ESCAPE_TIMER_MIN 0
3786 :
3787 : #define IWM_BA_ESCAPE_TIMER_DEFAULT 6
3788 : #define IWM_BA_ESCAPE_TIMER_D3 9
3789 : #define IWM_BA_ESCAPE_TIMER_MAX 1024
3790 : #define IWM_BA_ESCAPE_TIMER_MIN 0
3791 :
3792 : #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1
3793 :
3794 : #define IWM_BF_CMD_CONFIG_DEFAULTS \
3795 : .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \
3796 : .bf_roaming_energy_delta = \
3797 : htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \
3798 : .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \
3799 : .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \
3800 : .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \
3801 : .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \
3802 : .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \
3803 : .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \
3804 : .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT)
3805 :
3806 : /* uCode API values for HT/VHT bit rates */
3807 : #define IWM_RATE_HT_SISO_MCS_0_PLCP 0
3808 : #define IWM_RATE_HT_SISO_MCS_1_PLCP 1
3809 : #define IWM_RATE_HT_SISO_MCS_2_PLCP 2
3810 : #define IWM_RATE_HT_SISO_MCS_3_PLCP 3
3811 : #define IWM_RATE_HT_SISO_MCS_4_PLCP 4
3812 : #define IWM_RATE_HT_SISO_MCS_5_PLCP 5
3813 : #define IWM_RATE_HT_SISO_MCS_6_PLCP 6
3814 : #define IWM_RATE_HT_SISO_MCS_7_PLCP 7
3815 : #define IWM_RATE_HT_MIMO2_MCS_8_PLCP 0x8
3816 : #define IWM_RATE_HT_MIMO2_MCS_9_PLCP 0x9
3817 : #define IWM_RATE_HT_MIMO2_MCS_10_PLCP 0xA
3818 : #define IWM_RATE_HT_MIMO2_MCS_11_PLCP 0xB
3819 : #define IWM_RATE_HT_MIMO2_MCS_12_PLCP 0xC
3820 : #define IWM_RATE_HT_MIMO2_MCS_13_PLCP 0xD
3821 : #define IWM_RATE_HT_MIMO2_MCS_14_PLCP 0xE
3822 : #define IWM_RATE_HT_MIMO2_MCS_15_PLCP 0xF
3823 : #define IWM_RATE_VHT_SISO_MCS_0_PLCP 0
3824 : #define IWM_RATE_VHT_SISO_MCS_1_PLCP 1
3825 : #define IWM_RATE_VHT_SISO_MCS_2_PLCP 2
3826 : #define IWM_RATE_VHT_SISO_MCS_3_PLCP 3
3827 : #define IWM_RATE_VHT_SISO_MCS_4_PLCP 4
3828 : #define IWM_RATE_VHT_SISO_MCS_5_PLCP 5
3829 : #define IWM_RATE_VHT_SISO_MCS_6_PLCP 6
3830 : #define IWM_RATE_VHT_SISO_MCS_7_PLCP 7
3831 : #define IWM_RATE_VHT_SISO_MCS_8_PLCP 8
3832 : #define IWM_RATE_VHT_SISO_MCS_9_PLCP 9
3833 : #define IWM_RATE_VHT_MIMO2_MCS_0_PLCP 0x10
3834 : #define IWM_RATE_VHT_MIMO2_MCS_1_PLCP 0x11
3835 : #define IWM_RATE_VHT_MIMO2_MCS_2_PLCP 0x12
3836 : #define IWM_RATE_VHT_MIMO2_MCS_3_PLCP 0x13
3837 : #define IWM_RATE_VHT_MIMO2_MCS_4_PLCP 0x14
3838 : #define IWM_RATE_VHT_MIMO2_MCS_5_PLCP 0x15
3839 : #define IWM_RATE_VHT_MIMO2_MCS_6_PLCP 0x16
3840 : #define IWM_RATE_VHT_MIMO2_MCS_7_PLCP 0x17
3841 : #define IWM_RATE_VHT_MIMO2_MCS_8_PLCP 0x18
3842 : #define IWM_RATE_VHT_MIMO2_MCS_9_PLCP 0x19
3843 : #define IWM_RATE_HT_SISO_MCS_INV_PLCP 0x20
3844 : #define IWM_RATE_HT_MIMO2_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP
3845 : #define IWM_RATE_VHT_SISO_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP
3846 : #define IWM_RATE_VHT_MIMO2_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP
3847 : #define IWM_RATE_HT_SISO_MCS_8_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP
3848 : #define IWM_RATE_HT_SISO_MCS_9_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP
3849 :
3850 : /*
3851 : * These serve as indexes into struct iwm_rate iwm_rates[IWM_RIDX_MAX].
3852 : */
3853 : enum {
3854 : IWM_RATE_1M_INDEX = 0,
3855 : IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX,
3856 : IWM_RATE_2M_INDEX,
3857 : IWM_RATE_5M_INDEX,
3858 : IWM_RATE_11M_INDEX,
3859 : IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX,
3860 : IWM_RATE_6M_INDEX,
3861 : IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX,
3862 : IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX,
3863 : IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX,
3864 : IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX,
3865 : IWM_RATE_9M_INDEX,
3866 : IWM_RATE_12M_INDEX,
3867 : IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX,
3868 : IWM_RATE_MCS_8_INDEX,
3869 : IWM_FIRST_HT_MIMO2_RATE = IWM_RATE_MCS_8_INDEX,
3870 : IWM_RATE_18M_INDEX,
3871 : IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX,
3872 : IWM_RATE_24M_INDEX,
3873 : IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX,
3874 : IWM_RATE_MCS_9_INDEX,
3875 : IWM_RATE_36M_INDEX,
3876 : IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX,
3877 : IWM_RATE_MCS_10_INDEX,
3878 : IWM_RATE_48M_INDEX,
3879 : IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX,
3880 : IWM_RATE_MCS_11_INDEX,
3881 : IWM_RATE_54M_INDEX,
3882 : IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX,
3883 : IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX,
3884 : IWM_RATE_MCS_7_INDEX,
3885 : IWM_LAST_HT_SISO_RATE = IWM_RATE_MCS_7_INDEX,
3886 : IWM_RATE_MCS_12_INDEX,
3887 : IWM_RATE_MCS_13_INDEX,
3888 : IWM_RATE_MCS_14_INDEX,
3889 : IWM_RATE_MCS_15_INDEX,
3890 : IWM_LAST_HT_RATE = IWM_RATE_MCS_15_INDEX,
3891 : IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX,
3892 : IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1,
3893 : IWM_RATE_COUNT = IWM_LAST_HT_RATE + 1,
3894 : };
3895 :
3896 : #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX))
3897 :
3898 : /* fw API values for legacy bit rates, both OFDM and CCK */
3899 : #define IWM_RATE_6M_PLCP 13
3900 : #define IWM_RATE_9M_PLCP 15
3901 : #define IWM_RATE_12M_PLCP 5
3902 : #define IWM_RATE_18M_PLCP 7
3903 : #define IWM_RATE_24M_PLCP 9
3904 : #define IWM_RATE_36M_PLCP 11
3905 : #define IWM_RATE_48M_PLCP 1
3906 : #define IWM_RATE_54M_PLCP 3
3907 : #define IWM_RATE_1M_PLCP 10
3908 : #define IWM_RATE_2M_PLCP 20
3909 : #define IWM_RATE_5M_PLCP 55
3910 : #define IWM_RATE_11M_PLCP 110
3911 : #define IWM_RATE_INVM_PLCP 0xff
3912 :
3913 : /*
3914 : * rate_n_flags bit fields
3915 : *
3916 : * The 32-bit value has different layouts in the low 8 bites depending on the
3917 : * format. There are three formats, HT, VHT and legacy (11abg, with subformats
3918 : * for CCK and OFDM).
3919 : *
3920 : * High-throughput (HT) rate format
3921 : * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
3922 : * Very High-throughput (VHT) rate format
3923 : * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
3924 : * Legacy OFDM rate format for bits 7:0
3925 : * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
3926 : * Legacy CCK rate format for bits 7:0:
3927 : * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
3928 : */
3929 :
3930 : /* Bit 8: (1) HT format, (0) legacy or VHT format */
3931 : #define IWM_RATE_MCS_HT_POS 8
3932 : #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS)
3933 :
3934 : /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
3935 : #define IWM_RATE_MCS_CCK_POS 9
3936 : #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS)
3937 :
3938 : /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
3939 : #define IWM_RATE_MCS_VHT_POS 26
3940 : #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS)
3941 :
3942 :
3943 : /*
3944 : * High-throughput (HT) rate format for bits 7:0
3945 : *
3946 : * 2-0: MCS rate base
3947 : * 0) 6 Mbps
3948 : * 1) 12 Mbps
3949 : * 2) 18 Mbps
3950 : * 3) 24 Mbps
3951 : * 4) 36 Mbps
3952 : * 5) 48 Mbps
3953 : * 6) 54 Mbps
3954 : * 7) 60 Mbps
3955 : * 4-3: 0) Single stream (SISO)
3956 : * 1) Dual stream (MIMO)
3957 : * 2) Triple stream (MIMO)
3958 : * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
3959 : * (bits 7-6 are zero)
3960 : *
3961 : * Together the low 5 bits work out to the MCS index because we don't
3962 : * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
3963 : * streams and 16-23 have three streams. We could also support MCS 32
3964 : * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
3965 : */
3966 : #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7
3967 : #define IWM_RATE_HT_MCS_NSS_POS 3
3968 : #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS)
3969 :
3970 : /* Bit 10: (1) Use Green Field preamble */
3971 : #define IWM_RATE_HT_MCS_GF_POS 10
3972 : #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS)
3973 :
3974 : #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f
3975 :
3976 : /*
3977 : * Very High-throughput (VHT) rate format for bits 7:0
3978 : *
3979 : * 3-0: VHT MCS (0-9)
3980 : * 5-4: number of streams - 1:
3981 : * 0) Single stream (SISO)
3982 : * 1) Dual stream (MIMO)
3983 : * 2) Triple stream (MIMO)
3984 : */
3985 :
3986 : /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
3987 : #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf
3988 : #define IWM_RATE_VHT_MCS_NSS_POS 4
3989 : #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS)
3990 :
3991 : /*
3992 : * Legacy OFDM rate format for bits 7:0
3993 : *
3994 : * 3-0: 0xD) 6 Mbps
3995 : * 0xF) 9 Mbps
3996 : * 0x5) 12 Mbps
3997 : * 0x7) 18 Mbps
3998 : * 0x9) 24 Mbps
3999 : * 0xB) 36 Mbps
4000 : * 0x1) 48 Mbps
4001 : * 0x3) 54 Mbps
4002 : * (bits 7-4 are 0)
4003 : *
4004 : * Legacy CCK rate format for bits 7:0:
4005 : * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK):
4006 : *
4007 : * 6-0: 10) 1 Mbps
4008 : * 20) 2 Mbps
4009 : * 55) 5.5 Mbps
4010 : * 110) 11 Mbps
4011 : * (bit 7 is 0)
4012 : */
4013 : #define IWM_RATE_LEGACY_RATE_MSK 0xff
4014 :
4015 :
4016 : /*
4017 : * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
4018 : * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
4019 : */
4020 : #define IWM_RATE_MCS_CHAN_WIDTH_POS 11
4021 : #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4022 : #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4023 : #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4024 : #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4025 : #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4026 :
4027 : /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
4028 : #define IWM_RATE_MCS_SGI_POS 13
4029 : #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS)
4030 :
4031 : /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
4032 : #define IWM_RATE_MCS_ANT_POS 14
4033 : #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS)
4034 : #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS)
4035 : #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS)
4036 : #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \
4037 : IWM_RATE_MCS_ANT_B_MSK)
4038 : #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \
4039 : IWM_RATE_MCS_ANT_C_MSK)
4040 : #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK
4041 : #define IWM_RATE_MCS_ANT_NUM 3
4042 :
4043 : /* Bit 17-18: (0) SS, (1) SS*2 */
4044 : #define IWM_RATE_MCS_STBC_POS 17
4045 : #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS)
4046 :
4047 : /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
4048 : #define IWM_RATE_MCS_BF_POS 19
4049 : #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS)
4050 :
4051 : /* Bit 20: (0) ZLF is off, (1) ZLF is on */
4052 : #define IWM_RATE_MCS_ZLF_POS 20
4053 : #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS)
4054 :
4055 : /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
4056 : #define IWM_RATE_MCS_DUP_POS 24
4057 : #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS)
4058 :
4059 : /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
4060 : #define IWM_RATE_MCS_LDPC_POS 27
4061 : #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS)
4062 :
4063 :
4064 : /* Link Quality definitions */
4065 :
4066 : /* # entries in rate scale table to support Tx retries */
4067 : #define IWM_LQ_MAX_RETRY_NUM 16
4068 :
4069 : /* Link quality command flags bit fields */
4070 :
4071 : /* Bit 0: (0) Don't use RTS (1) Use RTS */
4072 : #define IWM_LQ_FLAG_USE_RTS_POS 0
4073 : #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS)
4074 :
4075 : /* Bit 1-3: LQ command color. Used to match responses to LQ commands */
4076 : #define IWM_LQ_FLAG_COLOR_POS 1
4077 : #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS)
4078 :
4079 : /* Bit 4-5: Tx RTS BW Signalling
4080 : * (0) No RTS BW signalling
4081 : * (1) Static BW signalling
4082 : * (2) Dynamic BW signalling
4083 : */
4084 : #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4
4085 : #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4086 : #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4087 : #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4088 :
4089 : /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
4090 : * Dyanmic BW selection allows Tx with narrower BW then requested in rates
4091 : */
4092 : #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6
4093 : #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS)
4094 :
4095 : /* Antenna flags. */
4096 : #define IWM_ANT_A (1 << 0)
4097 : #define IWM_ANT_B (1 << 1)
4098 : #define IWM_ANT_C (1 << 2)
4099 : /* Shortcuts. */
4100 : #define IWM_ANT_AB (IWM_ANT_A | IWM_ANT_B)
4101 : #define IWM_ANT_BC (IWM_ANT_B | IWM_ANT_C)
4102 : #define IWM_ANT_ABC (IWM_ANT_A | IWM_ANT_B | IWM_ANT_C)
4103 :
4104 : /**
4105 : * struct iwm_lq_cmd - link quality command
4106 : * @sta_id: station to update
4107 : * @control: not used
4108 : * @flags: combination of IWM_LQ_FLAG_*
4109 : * @mimo_delim: the first SISO index in rs_table, which separates MIMO
4110 : * and SISO rates
4111 : * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD).
4112 : * Should be IWM_ANT_[ABC]
4113 : * @dual_stream_ant_msk: best antennas for MIMO, combination of IWM_ANT_[ABC]
4114 : * @initial_rate_index: first index from rs_table per AC category
4115 : * @agg_time_limit: aggregation max time threshold in usec/100, meaning
4116 : * value of 100 is one usec. Range is 100 to 8000
4117 : * @agg_disable_start_th: try-count threshold for starting aggregation.
4118 : * If a frame has higher try-count, it should not be selected for
4119 : * starting an aggregation sequence.
4120 : * @agg_frame_cnt_limit: max frame count in an aggregation.
4121 : * 0: no limit
4122 : * 1: no aggregation (one frame per aggregation)
4123 : * 2 - 0x3f: maximal number of frames (up to 3f == 63)
4124 : * @rs_table: array of rates for each TX try, each is rate_n_flags,
4125 : * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP
4126 : * @bf_params: beam forming params, currently not used
4127 : */
4128 : struct iwm_lq_cmd {
4129 : uint8_t sta_id;
4130 : uint8_t reserved1;
4131 : uint16_t control;
4132 : /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */
4133 : uint8_t flags;
4134 : uint8_t mimo_delim;
4135 : uint8_t single_stream_ant_msk;
4136 : uint8_t dual_stream_ant_msk;
4137 : uint8_t initial_rate_index[IWM_AC_NUM];
4138 : /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */
4139 : uint16_t agg_time_limit;
4140 : uint8_t agg_disable_start_th;
4141 : uint8_t agg_frame_cnt_limit;
4142 : uint32_t reserved2;
4143 : uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM];
4144 : uint32_t bf_params;
4145 : }; /* LINK_QUALITY_CMD_API_S_VER_1 */
4146 :
4147 : /**
4148 : * bitmasks for tx_flags in TX command
4149 : * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
4150 : * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station
4151 : * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
4152 : * Otherwise, use rate_n_flags from the TX command
4153 : * @IWM_TX_CMD_FLG_BA: this frame is a block ack
4154 : * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected
4155 : * Must set IWM_TX_CMD_FLG_ACK with this flag.
4156 : * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection
4157 : * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence
4158 : * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence
4159 : * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC)
4160 : * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame
4161 : * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control.
4162 : * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
4163 : * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
4164 : * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame
4165 : * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame
4166 : * Should be set for beacons and probe responses
4167 : * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations
4168 : * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count
4169 : * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation
4170 : * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header.
4171 : * Should be set for 26/30 length MAC headers
4172 : * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW
4173 : * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration
4174 : * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation
4175 : * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id
4176 : * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped
4177 : * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD
4178 : * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power
4179 : * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk
4180 : */
4181 : #define IWM_TX_CMD_FLG_PROT_REQUIRE (1 << 0)
4182 : #define IWM_TX_CMD_FLG_ACK (1 << 3)
4183 : #define IWM_TX_CMD_FLG_STA_RATE (1 << 4)
4184 : #define IWM_TX_CMD_FLG_BA (1 << 5)
4185 : #define IWM_TX_CMD_FLG_BAR (1 << 6)
4186 : #define IWM_TX_CMD_FLG_TXOP_PROT (1 << 7)
4187 : #define IWM_TX_CMD_FLG_VHT_NDPA (1 << 8)
4188 : #define IWM_TX_CMD_FLG_HT_NDPA (1 << 9)
4189 : #define IWM_TX_CMD_FLG_CSI_FDBK2HOST (1 << 10)
4190 : #define IWM_TX_CMD_FLG_BT_DIS (1 << 12)
4191 : #define IWM_TX_CMD_FLG_SEQ_CTL (1 << 13)
4192 : #define IWM_TX_CMD_FLG_MORE_FRAG (1 << 14)
4193 : #define IWM_TX_CMD_FLG_NEXT_FRAME (1 << 15)
4194 : #define IWM_TX_CMD_FLG_TSF (1 << 16)
4195 : #define IWM_TX_CMD_FLG_CALIB (1 << 17)
4196 : #define IWM_TX_CMD_FLG_KEEP_SEQ_CTL (1 << 18)
4197 : #define IWM_TX_CMD_FLG_AGG_START (1 << 19)
4198 : #define IWM_TX_CMD_FLG_MH_PAD (1 << 20)
4199 : #define IWM_TX_CMD_FLG_RESP_TO_DRV (1 << 21)
4200 : #define IWM_TX_CMD_FLG_CCMP_AGG (1 << 22)
4201 : #define IWM_TX_CMD_FLG_TKIP_MIC_DONE (1 << 23)
4202 : #define IWM_TX_CMD_FLG_DUR (1 << 25)
4203 : #define IWM_TX_CMD_FLG_FW_DROP (1 << 26)
4204 : #define IWM_TX_CMD_FLG_EXEC_PAPD (1 << 27)
4205 : #define IWM_TX_CMD_FLG_PAPD_TYPE (1 << 28)
4206 : #define IWM_TX_CMD_FLG_HCCA_CHUNK (1 << 31)
4207 : /* IWM_TX_FLAGS_BITS_API_S_VER_1 */
4208 :
4209 : /*
4210 : * TX command security control
4211 : */
4212 : #define IWM_TX_CMD_SEC_WEP 0x01
4213 : #define IWM_TX_CMD_SEC_CCM 0x02
4214 : #define IWM_TX_CMD_SEC_TKIP 0x03
4215 : #define IWM_TX_CMD_SEC_EXT 0x04
4216 : #define IWM_TX_CMD_SEC_MSK 0x07
4217 : #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6
4218 : #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0
4219 : #define IWM_TX_CMD_SEC_KEY128 0x08
4220 :
4221 : /* TODO: how does these values are OK with only 16 bit variable??? */
4222 : /*
4223 : * TX command next frame info
4224 : *
4225 : * bits 0:2 - security control (IWM_TX_CMD_SEC_*)
4226 : * bit 3 - immediate ACK required
4227 : * bit 4 - rate is taken from STA table
4228 : * bit 5 - frame belongs to BA stream
4229 : * bit 6 - immediate BA response expected
4230 : * bit 7 - unused
4231 : * bits 8:15 - Station ID
4232 : * bits 16:31 - rate
4233 : */
4234 : #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8)
4235 : #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10)
4236 : #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20)
4237 : #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40)
4238 : #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8)
4239 : #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00)
4240 : #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8)
4241 : #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000)
4242 : #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16)
4243 :
4244 : /*
4245 : * TX command Frame life time in us - to be written in pm_frame_timeout
4246 : */
4247 : #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF
4248 : #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/
4249 : #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */
4250 : #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0
4251 :
4252 : /*
4253 : * TID for non QoS frames - to be written in tid_tspec
4254 : */
4255 : #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT
4256 :
4257 : /*
4258 : * Limits on the retransmissions - to be written in {data,rts}_retry_limit
4259 : */
4260 : #define IWM_DEFAULT_TX_RETRY 15
4261 : #define IWM_MGMT_DFAULT_RETRY_LIMIT 3
4262 : #define IWM_RTS_DFAULT_RETRY_LIMIT 3
4263 : #define IWM_BAR_DFAULT_RETRY_LIMIT 60
4264 : #define IWM_LOW_RETRY_LIMIT 7
4265 :
4266 : /* TODO: complete documentation for try_cnt and btkill_cnt */
4267 : /**
4268 : * struct iwm_tx_cmd - TX command struct to FW
4269 : * ( IWM_TX_CMD = 0x1c )
4270 : * @len: in bytes of the payload, see below for details
4271 : * @next_frame_len: same as len, but for next frame (0 if not applicable)
4272 : * Used for fragmentation and bursting, but not in 11n aggregation.
4273 : * @tx_flags: combination of IWM_TX_CMD_FLG_*
4274 : * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is
4275 : * cleared. Combination of IWM_RATE_MCS_*
4276 : * @sta_id: index of destination station in FW station table
4277 : * @sec_ctl: security control, IWM_TX_CMD_SEC_*
4278 : * @initial_rate_index: index into the rate table for initial TX attempt.
4279 : * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames.
4280 : * @key: security key
4281 : * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_*
4282 : * @life_time: frame life time (usecs??)
4283 : * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt +
4284 : * btkill_cnd + reserved), first 32 bits. "0" disables usage.
4285 : * @dram_msb_ptr: upper bits of the scratch physical address
4286 : * @rts_retry_limit: max attempts for RTS
4287 : * @data_retry_limit: max attempts to send the data packet
4288 : * @tid_spec: TID/tspec
4289 : * @pm_frame_timeout: PM TX frame timeout
4290 : * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not
4291 : * specified by HCCA protocol
4292 : *
4293 : * The byte count (both len and next_frame_len) includes MAC header
4294 : * (24/26/30/32 bytes)
4295 : * + 2 bytes pad if 26/30 header size
4296 : * + 8 byte IV for CCM or TKIP (not used for WEP)
4297 : * + Data payload
4298 : * + 8-byte MIC (not used for CCM/WEP)
4299 : * It does not include post-MAC padding, i.e.,
4300 : * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes.
4301 : * Range of len: 14-2342 bytes.
4302 : *
4303 : * After the struct fields the MAC header is placed, plus any padding,
4304 : * and then the actial payload.
4305 : */
4306 : struct iwm_tx_cmd {
4307 : uint16_t len;
4308 : uint16_t next_frame_len;
4309 : uint32_t tx_flags;
4310 : struct {
4311 : uint8_t try_cnt;
4312 : uint8_t btkill_cnt;
4313 : uint16_t reserved;
4314 : } scratch; /* DRAM_SCRATCH_API_U_VER_1 */
4315 : uint32_t rate_n_flags;
4316 : uint8_t sta_id;
4317 : uint8_t sec_ctl;
4318 : uint8_t initial_rate_index;
4319 : uint8_t reserved2;
4320 : uint8_t key[16];
4321 : uint16_t next_frame_flags;
4322 : uint16_t reserved3;
4323 : uint32_t life_time;
4324 : uint32_t dram_lsb_ptr;
4325 : uint8_t dram_msb_ptr;
4326 : uint8_t rts_retry_limit;
4327 : uint8_t data_retry_limit;
4328 : uint8_t tid_tspec;
4329 : uint16_t pm_frame_timeout;
4330 : uint16_t driver_txop;
4331 : uint8_t payload[0];
4332 : struct ieee80211_frame hdr[0];
4333 : } __packed; /* IWM_TX_CMD_API_S_VER_3 */
4334 :
4335 : /*
4336 : * TX response related data
4337 : */
4338 :
4339 : /*
4340 : * status that is returned by the fw after attempts to Tx
4341 : * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and
4342 : * STA table
4343 : * Valid only if frame_count =1
4344 : */
4345 : #define IWM_TX_STATUS_MSK 0x000000ff
4346 : #define IWM_TX_STATUS_SUCCESS 0x01
4347 : #define IWM_TX_STATUS_DIRECT_DONE 0x02
4348 : /* postpone TX */
4349 : #define IWM_TX_STATUS_POSTPONE_DELAY 0x40
4350 : #define IWM_TX_STATUS_POSTPONE_FEW_BYTES 0x41
4351 : #define IWM_TX_STATUS_POSTPONE_BT_PRIO 0x42
4352 : #define IWM_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43
4353 : #define IWM_TX_STATUS_POSTPONE_CALC_TTAK 0x44
4354 : /* abort TX */
4355 : #define IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81
4356 : #define IWM_TX_STATUS_FAIL_SHORT_LIMIT 0x82
4357 : #define IWM_TX_STATUS_FAIL_LONG_LIMIT 0x83
4358 : #define IWM_TX_STATUS_FAIL_UNDERRUN 0x84
4359 : #define IWM_TX_STATUS_FAIL_DRAIN_FLOW 0x85
4360 : #define IWM_TX_STATUS_FAIL_RFKILL_FLUSH 0x86
4361 : #define IWM_TX_STATUS_FAIL_LIFE_EXPIRE 0x87
4362 : #define IWM_TX_STATUS_FAIL_DEST_PS 0x88
4363 : #define IWM_TX_STATUS_FAIL_HOST_ABORTED 0x89
4364 : #define IWM_TX_STATUS_FAIL_BT_RETRY 0x8a
4365 : #define IWM_TX_STATUS_FAIL_STA_INVALID 0x8b
4366 : #define IWM_TX_STATUS_FAIL_FRAG_DROPPED 0x8c
4367 : #define IWM_TX_STATUS_FAIL_TID_DISABLE 0x8d
4368 : #define IWM_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e
4369 : #define IWM_TX_STATUS_FAIL_SMALL_CF_POLL 0x8f
4370 : #define IWM_TX_STATUS_FAIL_FW_DROP 0x90
4371 : #define IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH 0x91
4372 : #define IWM_TX_STATUS_INTERNAL_ABORT 0x92
4373 : #define IWM_TX_MODE_MSK 0x00000f00
4374 : #define IWM_TX_MODE_NO_BURST 0x00000000
4375 : #define IWM_TX_MODE_IN_BURST_SEQ 0x00000100
4376 : #define IWM_TX_MODE_FIRST_IN_BURST 0x00000200
4377 : #define IWM_TX_QUEUE_NUM_MSK 0x0001f000
4378 : #define IWM_TX_NARROW_BW_MSK 0x00060000
4379 : #define IWM_TX_NARROW_BW_1DIV2 0x00020000
4380 : #define IWM_TX_NARROW_BW_1DIV4 0x00040000
4381 : #define IWM_TX_NARROW_BW_1DIV8 0x00060000
4382 :
4383 : /*
4384 : * TX aggregation status
4385 : * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries
4386 : * occur if tx failed for this frame when it was a member of a previous
4387 : * aggregation block). If rate scaling is used, retry count indicates the
4388 : * rate table entry used for all frames in the new agg.
4389 : * @IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for
4390 : * this frame
4391 : */
4392 : #define IWM_AGG_TX_STATE_STATUS_MSK 0x0fff
4393 : #define IWM_AGG_TX_STATE_TRANSMITTED 0x0000
4394 : #define IWM_AGG_TX_STATE_UNDERRUN 0x0001
4395 : #define IWM_AGG_TX_STATE_BT_PRIO 0x0002
4396 : #define IWM_AGG_TX_STATE_FEW_BYTES 0x0004
4397 : #define IWM_AGG_TX_STATE_ABORT 0x0008
4398 : #define IWM_AGG_TX_STATE_LAST_SENT_TTL 0x0010
4399 : #define IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT 0x0020
4400 : #define IWM_AGG_TX_STATE_LAST_SENT_BT_KILL 0x0040
4401 : #define IWM_AGG_TX_STATE_SCD_QUERY 0x0080
4402 : #define IWM_AGG_TX_STATE_TEST_BAD_CRC32 0x0100
4403 : #define IWM_AGG_TX_STATE_RESPONSE 0x01ff
4404 : #define IWM_AGG_TX_STATE_DUMP_TX 0x0200
4405 : #define IWM_AGG_TX_STATE_DELAY_TX 0x0400
4406 : #define IWM_AGG_TX_STATE_TRY_CNT_POS 12
4407 : #define IWM_AGG_TX_STATE_TRY_CNT_MSK (0xf << IWM_AGG_TX_STATE_TRY_CNT_POS)
4408 :
4409 : #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \
4410 : IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \
4411 : IWM_AGG_TX_STATE_LAST_SENT_BT_KILL)
4412 :
4413 : /*
4414 : * The mask below describes a status where we are absolutely sure that the MPDU
4415 : * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've
4416 : * written the bytes to the TXE, but we know nothing about what the DSP did.
4417 : */
4418 : #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \
4419 : IWM_AGG_TX_STATE_ABORT | \
4420 : IWM_AGG_TX_STATE_SCD_QUERY)
4421 :
4422 : /*
4423 : * IWM_REPLY_TX = 0x1c (response)
4424 : *
4425 : * This response may be in one of two slightly different formats, indicated
4426 : * by the frame_count field:
4427 : *
4428 : * 1) No aggregation (frame_count == 1). This reports Tx results for a single
4429 : * frame. Multiple attempts, at various bit rates, may have been made for
4430 : * this frame.
4431 : *
4432 : * 2) Aggregation (frame_count > 1). This reports Tx results for two or more
4433 : * frames that used block-acknowledge. All frames were transmitted at
4434 : * same rate. Rate scaling may have been used if first frame in this new
4435 : * agg block failed in previous agg block(s).
4436 : *
4437 : * Note that, for aggregation, ACK (block-ack) status is not delivered
4438 : * here; block-ack has not been received by the time the device records
4439 : * this status.
4440 : * This status relates to reasons the tx might have been blocked or aborted
4441 : * within the device, rather than whether it was received successfully by
4442 : * the destination station.
4443 : */
4444 :
4445 : /**
4446 : * struct iwm_agg_tx_status - per packet TX aggregation status
4447 : * @status: enum iwm_tx_agg_status
4448 : * @sequence: Sequence # for this frame's Tx cmd (not SSN!)
4449 : */
4450 : struct iwm_agg_tx_status {
4451 : uint16_t status;
4452 : uint16_t sequence;
4453 : } __packed;
4454 :
4455 : /*
4456 : * definitions for initial rate index field
4457 : * bits [3:0] initial rate index
4458 : * bits [6:4] rate table color, used for the initial rate
4459 : * bit-7 invalid rate indication
4460 : */
4461 : #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f
4462 : #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70
4463 : #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80
4464 :
4465 : #define IWM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f)
4466 : #define IWM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4)
4467 :
4468 : /**
4469 : * struct iwm_tx_resp - notifies that fw is TXing a packet
4470 : * ( IWM_REPLY_TX = 0x1c )
4471 : * @frame_count: 1 no aggregation, >1 aggregation
4472 : * @bt_kill_count: num of times blocked by bluetooth (unused for agg)
4473 : * @failure_rts: num of failures due to unsuccessful RTS
4474 : * @failure_frame: num failures due to no ACK (unused for agg)
4475 : * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the
4476 : * Tx of all the batch. IWM_RATE_MCS_*
4477 : * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK.
4478 : * for agg: RTS + CTS + aggregation tx time + block-ack time.
4479 : * in usec.
4480 : * @pa_status: tx power info
4481 : * @pa_integ_res_a: tx power info
4482 : * @pa_integ_res_b: tx power info
4483 : * @pa_integ_res_c: tx power info
4484 : * @measurement_req_id: tx power info
4485 : * @tfd_info: TFD information set by the FH
4486 : * @seq_ctl: sequence control from the Tx cmd
4487 : * @byte_cnt: byte count from the Tx cmd
4488 : * @tlc_info: TLC rate info
4489 : * @ra_tid: bits [3:0] = ra, bits [7:4] = tid
4490 : * @frame_ctrl: frame control
4491 : * @status: for non-agg: frame status IWM_TX_STATUS_*
4492 : * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields
4493 : * follow this one, up to frame_count.
4494 : *
4495 : * After the array of statuses comes the SSN of the SCD. Look at
4496 : * %iwm_get_scd_ssn for more details.
4497 : */
4498 : struct iwm_tx_resp {
4499 : uint8_t frame_count;
4500 : uint8_t bt_kill_count;
4501 : uint8_t failure_rts;
4502 : uint8_t failure_frame;
4503 : uint32_t initial_rate;
4504 : uint16_t wireless_media_time;
4505 :
4506 : uint8_t pa_status;
4507 : uint8_t pa_integ_res_a[3];
4508 : uint8_t pa_integ_res_b[3];
4509 : uint8_t pa_integ_res_c[3];
4510 : uint16_t measurement_req_id;
4511 : uint16_t reserved;
4512 :
4513 : uint32_t tfd_info;
4514 : uint16_t seq_ctl;
4515 : uint16_t byte_cnt;
4516 : uint8_t tlc_info;
4517 : uint8_t ra_tid;
4518 : uint16_t frame_ctrl;
4519 :
4520 : struct iwm_agg_tx_status status;
4521 : } __packed; /* IWM_TX_RSP_API_S_VER_3 */
4522 :
4523 : /**
4524 : * struct iwm_ba_notif - notifies about reception of BA
4525 : * ( IWM_BA_NOTIF = 0xc5 )
4526 : * @sta_addr_lo32: lower 32 bits of the MAC address
4527 : * @sta_addr_hi16: upper 16 bits of the MAC address
4528 : * @sta_id: Index of recipient (BA-sending) station in fw's station table
4529 : * @tid: tid of the session
4530 : * @seq_ctl:
4531 : * @bitmap: the bitmap of the BA notification as seen in the air
4532 : * @scd_flow: the tx queue this BA relates to
4533 : * @scd_ssn: the index of the last contiguously sent packet
4534 : * @txed: number of Txed frames in this batch
4535 : * @txed_2_done: number of Acked frames in this batch
4536 : */
4537 : struct iwm_ba_notif {
4538 : uint32_t sta_addr_lo32;
4539 : uint16_t sta_addr_hi16;
4540 : uint16_t reserved;
4541 :
4542 : uint8_t sta_id;
4543 : uint8_t tid;
4544 : uint16_t seq_ctl;
4545 : uint64_t bitmap;
4546 : uint16_t scd_flow;
4547 : uint16_t scd_ssn;
4548 : uint8_t txed;
4549 : uint8_t txed_2_done;
4550 : uint16_t reserved1;
4551 : } __packed;
4552 :
4553 : /*
4554 : * struct iwm_mac_beacon_cmd - beacon template command
4555 : * @tx: the tx commands associated with the beacon frame
4556 : * @template_id: currently equal to the mac context id of the coresponding
4557 : * mac.
4558 : * @tim_idx: the offset of the tim IE in the beacon
4559 : * @tim_size: the length of the tim IE
4560 : * @frame: the template of the beacon frame
4561 : */
4562 : struct iwm_mac_beacon_cmd {
4563 : struct iwm_tx_cmd tx;
4564 : uint32_t template_id;
4565 : uint32_t tim_idx;
4566 : uint32_t tim_size;
4567 : struct ieee80211_frame frame[0];
4568 : } __packed;
4569 :
4570 : struct iwm_beacon_notif {
4571 : struct iwm_tx_resp beacon_notify_hdr;
4572 : uint64_t tsf;
4573 : uint32_t ibss_mgr_status;
4574 : } __packed;
4575 :
4576 : /**
4577 : * dump (flush) control flags
4578 : * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty
4579 : * and the TFD queues are empty.
4580 : */
4581 : #define IWM_DUMP_TX_FIFO_FLUSH (1 << 1)
4582 :
4583 : /**
4584 : * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command
4585 : * @queues_ctl: bitmap of queues to flush
4586 : * @flush_ctl: control flags
4587 : * @reserved: reserved
4588 : */
4589 : struct iwm_tx_path_flush_cmd {
4590 : uint32_t queues_ctl;
4591 : uint16_t flush_ctl;
4592 : uint16_t reserved;
4593 : } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */
4594 :
4595 : /**
4596 : * iwm_get_scd_ssn - returns the SSN of the SCD
4597 : * @tx_resp: the Tx response from the fw (agg or non-agg)
4598 : *
4599 : * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since
4600 : * it can't know that everything will go well until the end of the AMPDU, it
4601 : * can't know in advance the number of MPDUs that will be sent in the current
4602 : * batch. This is why it writes the agg Tx response while it fetches the MPDUs.
4603 : * Hence, it can't know in advance what the SSN of the SCD will be at the end
4604 : * of the batch. This is why the SSN of the SCD is written at the end of the
4605 : * whole struct at a variable offset. This function knows how to cope with the
4606 : * variable offset and returns the SSN of the SCD.
4607 : */
4608 : static inline uint32_t iwm_get_scd_ssn(struct iwm_tx_resp *tx_resp)
4609 : {
4610 : return le32_to_cpup((uint32_t *)&tx_resp->status +
4611 : tx_resp->frame_count) & 0xfff;
4612 : }
4613 :
4614 : /**
4615 : * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command
4616 : * @token:
4617 : * @sta_id: station id
4618 : * @tid:
4619 : * @scd_queue: scheduler queue to confiug
4620 : * @enable: 1 queue enable, 0 queue disable
4621 : * @aggregate: 1 aggregated queue, 0 otherwise
4622 : * @tx_fifo: %enum iwm_tx_fifo
4623 : * @window: BA window size
4624 : * @ssn: SSN for the BA agreement
4625 : */
4626 : struct iwm_scd_txq_cfg_cmd {
4627 : uint8_t token;
4628 : uint8_t sta_id;
4629 : uint8_t tid;
4630 : uint8_t scd_queue;
4631 : uint8_t enable;
4632 : uint8_t aggregate;
4633 : uint8_t tx_fifo;
4634 : uint8_t window;
4635 : uint16_t ssn;
4636 : uint16_t reserved;
4637 : } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */
4638 :
4639 : /**
4640 : * struct iwm_scd_txq_cfg_rsp
4641 : * @token: taken from the command
4642 : * @sta_id: station id from the command
4643 : * @tid: tid from the command
4644 : * @scd_queue: scd_queue from the command
4645 : */
4646 : struct iwm_scd_txq_cfg_rsp {
4647 : uint8_t token;
4648 : uint8_t sta_id;
4649 : uint8_t tid;
4650 : uint8_t scd_queue;
4651 : } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */
4652 :
4653 :
4654 : /* Scan Commands, Responses, Notifications */
4655 :
4656 : /* Max number of IEs for direct SSID scans in a command */
4657 : #define IWM_PROBE_OPTION_MAX 20
4658 :
4659 : /**
4660 : * struct iwm_ssid_ie - directed scan network information element
4661 : *
4662 : * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD,
4663 : * selected by "type" bit field in struct iwm_scan_channel;
4664 : * each channel may select different ssids from among the 20 entries.
4665 : * SSID IEs get transmitted in reverse order of entry.
4666 : */
4667 : struct iwm_ssid_ie {
4668 : uint8_t id;
4669 : uint8_t len;
4670 : uint8_t ssid[IEEE80211_NWID_LEN];
4671 : } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
4672 :
4673 : /* scan offload */
4674 : #define IWM_SCAN_MAX_BLACKLIST_LEN 64
4675 : #define IWM_SCAN_SHORT_BLACKLIST_LEN 16
4676 : #define IWM_SCAN_MAX_PROFILES 11
4677 : #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512
4678 :
4679 : /* Default watchdog (in MS) for scheduled scan iteration */
4680 : #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000)
4681 :
4682 : #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
4683 : #define IWM_CAN_ABORT_STATUS 1
4684 :
4685 : #define IWM_FULL_SCAN_MULTIPLIER 5
4686 : #define IWM_FAST_SCHED_SCAN_ITERATIONS 3
4687 : #define IWM_MAX_SCHED_SCAN_PLANS 2
4688 :
4689 : /**
4690 : * iwm_scan_schedule_lmac - schedule of scan offload
4691 : * @delay: delay between iterations, in seconds.
4692 : * @iterations: num of scan iterations
4693 : * @full_scan_mul: number of partial scans before each full scan
4694 : */
4695 : struct iwm_scan_schedule_lmac {
4696 : uint16_t delay;
4697 : uint8_t iterations;
4698 : uint8_t full_scan_mul;
4699 : } __packed; /* SCAN_SCHEDULE_API_S */
4700 :
4701 : /**
4702 : * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S
4703 : * @tx_flags: combination of TX_CMD_FLG_*
4704 : * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is
4705 : * cleared. Combination of RATE_MCS_*
4706 : * @sta_id: index of destination station in FW station table
4707 : * @reserved: for alignment and future use
4708 : */
4709 : struct iwm_scan_req_tx_cmd {
4710 : uint32_t tx_flags;
4711 : uint32_t rate_n_flags;
4712 : uint8_t sta_id;
4713 : uint8_t reserved[3];
4714 : } __packed;
4715 :
4716 : #define IWM_UNIFIED_SCAN_CHANNEL_FULL (1 << 27)
4717 : #define IWM_UNIFIED_SCAN_CHANNEL_PARTIAL (1 << 28)
4718 :
4719 : /**
4720 : * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2
4721 : * @flags: bits 1-20: directed scan to i'th ssid
4722 : * other bits &enum iwm_scan_channel_flags_lmac
4723 : * @channel_number: channel number 1-13 etc
4724 : * @iter_count: scan iteration on this channel
4725 : * @iter_interval: interval in seconds between iterations on one channel
4726 : */
4727 : struct iwm_scan_channel_cfg_lmac {
4728 : uint32_t flags;
4729 : uint16_t channel_num;
4730 : uint16_t iter_count;
4731 : uint32_t iter_interval;
4732 : } __packed;
4733 :
4734 : /*
4735 : * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1
4736 : * @offset: offset in the data block
4737 : * @len: length of the segment
4738 : */
4739 : struct iwm_scan_probe_segment {
4740 : uint16_t offset;
4741 : uint16_t len;
4742 : } __packed;
4743 :
4744 : /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2
4745 : * @mac_header: first (and common) part of the probe
4746 : * @band_data: band specific data
4747 : * @common_data: last (and common) part of the probe
4748 : * @buf: raw data block
4749 : */
4750 : struct iwm_scan_probe_req {
4751 : struct iwm_scan_probe_segment mac_header;
4752 : struct iwm_scan_probe_segment band_data[2];
4753 : struct iwm_scan_probe_segment common_data;
4754 : uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE];
4755 : } __packed;
4756 :
4757 : #define IWM_SCAN_CHANNEL_FLAG_EBS (1 << 0)
4758 : #define IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE (1 << 1)
4759 : #define IWM_SCAN_CHANNEL_FLAG_CACHE_ADD (1 << 2)
4760 :
4761 : /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S
4762 : * @flags: enum iwm_scan_channel_flags
4763 : * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is
4764 : * involved.
4765 : * 1 - EBS is disabled.
4766 : * 2 - every second scan will be full scan(and so on).
4767 : */
4768 : struct iwm_scan_channel_opt {
4769 : uint16_t flags;
4770 : uint16_t non_ebs_ratio;
4771 : } __packed;
4772 :
4773 : /**
4774 : * LMAC scan flags
4775 : * @IWM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses
4776 : * without filtering.
4777 : * @IWM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels
4778 : * @IWM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan
4779 : * @IWM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification
4780 : * @IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching
4781 : * @IWM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented
4782 : * @IWM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report
4783 : * and DS parameter set IEs into probe requests.
4784 : * @IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels
4785 : * 1, 6 and 11.
4786 : * @IWM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches
4787 : */
4788 : #define IWM_LMAC_SCAN_FLAG_PASS_ALL (1 << 0)
4789 : #define IWM_LMAC_SCAN_FLAG_PASSIVE (1 << 1)
4790 : #define IWM_LMAC_SCAN_FLAG_PRE_CONNECTION (1 << 2)
4791 : #define IWM_LMAC_SCAN_FLAG_ITER_COMPLETE (1 << 3)
4792 : #define IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS (1 << 4)
4793 : #define IWM_LMAC_SCAN_FLAG_FRAGMENTED (1 << 5)
4794 : #define IWM_LMAC_SCAN_FLAGS_RRM_ENABLED (1 << 6)
4795 : #define IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL (1 << 7)
4796 : #define IWM_LMAC_SCAN_FLAG_MATCH (1 << 9)
4797 :
4798 : #define IWM_SCAN_PRIORITY_LOW 0
4799 : #define IWM_SCAN_PRIORITY_MEDIUM 1
4800 : #define IWM_SCAN_PRIORITY_HIGH 2
4801 :
4802 : /**
4803 : * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1
4804 : * @reserved1: for alignment and future use
4805 : * @channel_num: num of channels to scan
4806 : * @active-dwell: dwell time for active channels
4807 : * @passive-dwell: dwell time for passive channels
4808 : * @fragmented-dwell: dwell time for fragmented passive scan
4809 : * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases)
4810 : * @reserved2: for alignment and future use
4811 : * @rx_chain_selct: PHY_RX_CHAIN_* flags
4812 : * @scan_flags: &enum iwm_lmac_scan_flags
4813 : * @max_out_time: max time (in TU) to be out of associated channel
4814 : * @suspend_time: pause scan this long (TUs) when returning to service channel
4815 : * @flags: RXON flags
4816 : * @filter_flags: RXON filter
4817 : * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz
4818 : * @direct_scan: list of SSIDs for directed active scan
4819 : * @scan_prio: enum iwm_scan_priority
4820 : * @iter_num: number of scan iterations
4821 : * @delay: delay in seconds before first iteration
4822 : * @schedule: two scheduling plans. The first one is finite, the second one can
4823 : * be infinite.
4824 : * @channel_opt: channel optimization options, for full and partial scan
4825 : * @data: channel configuration and probe request packet.
4826 : */
4827 : struct iwm_scan_req_lmac {
4828 : /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */
4829 : uint32_t reserved1;
4830 : uint8_t n_channels;
4831 : uint8_t active_dwell;
4832 : uint8_t passive_dwell;
4833 : uint8_t fragmented_dwell;
4834 : uint8_t extended_dwell;
4835 : uint8_t reserved2;
4836 : uint16_t rx_chain_select;
4837 : uint32_t scan_flags;
4838 : uint32_t max_out_time;
4839 : uint32_t suspend_time;
4840 : /* RX_ON_FLAGS_API_S_VER_1 */
4841 : uint32_t flags;
4842 : uint32_t filter_flags;
4843 : struct iwm_scan_req_tx_cmd tx_cmd[2];
4844 : struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
4845 : uint32_t scan_prio;
4846 : /* SCAN_REQ_PERIODIC_PARAMS_API_S */
4847 : uint32_t iter_num;
4848 : uint32_t delay;
4849 : struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS];
4850 : struct iwm_scan_channel_opt channel_opt[2];
4851 : uint8_t data[];
4852 : } __packed;
4853 :
4854 : /**
4855 : * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2
4856 : * @last_schedule_line: last schedule line executed (fast or regular)
4857 : * @last_schedule_iteration: last scan iteration executed before scan abort
4858 : * @status: enum iwm_scan_offload_complete_status
4859 : * @ebs_status: EBS success status &enum iwm_scan_ebs_status
4860 : * @time_after_last_iter; time in seconds elapsed after last iteration
4861 : */
4862 : struct iwm_periodic_scan_complete {
4863 : uint8_t last_schedule_line;
4864 : uint8_t last_schedule_iteration;
4865 : uint8_t status;
4866 : uint8_t ebs_status;
4867 : uint32_t time_after_last_iter;
4868 : uint32_t reserved;
4869 : } __packed;
4870 :
4871 : /**
4872 : * struct iwm_scan_results_notif - scan results for one channel -
4873 : * SCAN_RESULT_NTF_API_S_VER_3
4874 : * @channel: which channel the results are from
4875 : * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
4876 : * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request
4877 : * @num_probe_not_sent: # of request that weren't sent due to not enough time
4878 : * @duration: duration spent in channel, in usecs
4879 : */
4880 : struct iwm_scan_results_notif {
4881 : uint8_t channel;
4882 : uint8_t band;
4883 : uint8_t probe_status;
4884 : uint8_t num_probe_not_sent;
4885 : uint32_t duration;
4886 : } __packed;
4887 :
4888 : #define IWM_SCAN_CLIENT_SCHED_SCAN (1 << 0)
4889 : #define IWM_SCAN_CLIENT_NETDETECT (1 << 1)
4890 : #define IWM_SCAN_CLIENT_ASSET_TRACKING (1 << 2)
4891 :
4892 : /**
4893 : * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S
4894 : * @ssid: MAC address to filter out
4895 : * @reported_rssi: AP rssi reported to the host
4896 : * @client_bitmap: clients ignore this entry - enum scan_framework_client
4897 : */
4898 : struct iwm_scan_offload_blacklist {
4899 : uint8_t ssid[ETHER_ADDR_LEN];
4900 : uint8_t reported_rssi;
4901 : uint8_t client_bitmap;
4902 : } __packed;
4903 :
4904 : #define IWM_NETWORK_TYPE_BSS 1
4905 : #define IWM_NETWORK_TYPE_IBSS 2
4906 : #define IWM_NETWORK_TYPE_ANY 3
4907 :
4908 : #define IWM_SCAN_OFFLOAD_SELECT_2_4 0x4
4909 : #define IWM_SCAN_OFFLOAD_SELECT_5_2 0x8
4910 : #define IWM_SCAN_OFFLOAD_SELECT_ANY 0xc
4911 :
4912 : /**
4913 : * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S
4914 : * @ssid_index: index to ssid list in fixed part
4915 : * @unicast_cipher: encryption olgorithm to match - bitmap
4916 : * @aut_alg: authentication olgorithm to match - bitmap
4917 : * @network_type: enum iwm_scan_offload_network_type
4918 : * @band_selection: enum iwm_scan_offload_band_selection
4919 : * @client_bitmap: clients waiting for match - enum scan_framework_client
4920 : */
4921 : struct iwm_scan_offload_profile {
4922 : uint8_t ssid_index;
4923 : uint8_t unicast_cipher;
4924 : uint8_t auth_alg;
4925 : uint8_t network_type;
4926 : uint8_t band_selection;
4927 : uint8_t client_bitmap;
4928 : uint8_t reserved[2];
4929 : } __packed;
4930 :
4931 : /**
4932 : * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1
4933 : * @blaclist: AP list to filter off from scan results
4934 : * @profiles: profiles to search for match
4935 : * @blacklist_len: length of blacklist
4936 : * @num_profiles: num of profiles in the list
4937 : * @match_notify: clients waiting for match found notification
4938 : * @pass_match: clients waiting for the results
4939 : * @active_clients: active clients bitmap - enum scan_framework_client
4940 : * @any_beacon_notify: clients waiting for match notification without match
4941 : */
4942 : struct iwm_scan_offload_profile_cfg {
4943 : struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES];
4944 : uint8_t blacklist_len;
4945 : uint8_t num_profiles;
4946 : uint8_t match_notify;
4947 : uint8_t pass_match;
4948 : uint8_t active_clients;
4949 : uint8_t any_beacon_notify;
4950 : uint8_t reserved[2];
4951 : } __packed;
4952 :
4953 : #define IWM_SCAN_OFFLOAD_COMPLETED 1
4954 : #define IWM_SCAN_OFFLOAD_ABORTED 2
4955 :
4956 : /**
4957 : * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels)
4958 : * SCAN_COMPLETE_NTF_API_S_VER_3
4959 : * @scanned_channels: number of channels scanned (and number of valid results)
4960 : * @status: one of SCAN_COMP_STATUS_*
4961 : * @bt_status: BT on/off status
4962 : * @last_channel: last channel that was scanned
4963 : * @tsf_low: TSF timer (lower half) in usecs
4964 : * @tsf_high: TSF timer (higher half) in usecs
4965 : * @results: an array of scan results, only "scanned_channels" of them are valid
4966 : */
4967 : struct iwm_lmac_scan_complete_notif {
4968 : uint8_t scanned_channels;
4969 : uint8_t status;
4970 : uint8_t bt_status;
4971 : uint8_t last_channel;
4972 : uint32_t tsf_low;
4973 : uint32_t tsf_high;
4974 : struct iwm_scan_results_notif results[];
4975 : } __packed;
4976 :
4977 :
4978 : /* UMAC Scan API */
4979 :
4980 : /* The maximum of either of these cannot exceed 8, because we use an
4981 : * 8-bit mask (see IWM_SCAN_MASK).
4982 : */
4983 : #define IWM_MAX_UMAC_SCANS 8
4984 : #define IWM_MAX_LMAC_SCANS 1
4985 :
4986 : #define IWM_SCAN_CONFIG_FLAG_ACTIVATE (1 << 0)
4987 : #define IWM_SCAN_CONFIG_FLAG_DEACTIVATE (1 << 1)
4988 : #define IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS (1 << 2)
4989 : #define IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS (1 << 3)
4990 : #define IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS (1 << 8)
4991 : #define IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS (1 << 9)
4992 : #define IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID (1 << 10)
4993 : #define IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES (1 << 11)
4994 : #define IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES (1 << 12)
4995 : #define IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS (1 << 13)
4996 : #define IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES (1 << 14)
4997 : #define IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR (1 << 15)
4998 : #define IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED (1 << 16)
4999 : #define IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED (1 << 17)
5000 : #define IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE (1 << 18)
5001 : #define IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE (1 << 19)
5002 : #define IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE (1 << 20)
5003 : #define IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE (1 << 21)
5004 :
5005 : /* Bits 26-31 are for num of channels in channel_array */
5006 : #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26)
5007 :
5008 : /* OFDM basic rates */
5009 : #define IWM_SCAN_CONFIG_RATE_6M (1 << 0)
5010 : #define IWM_SCAN_CONFIG_RATE_9M (1 << 1)
5011 : #define IWM_SCAN_CONFIG_RATE_12M (1 << 2)
5012 : #define IWM_SCAN_CONFIG_RATE_18M (1 << 3)
5013 : #define IWM_SCAN_CONFIG_RATE_24M (1 << 4)
5014 : #define IWM_SCAN_CONFIG_RATE_36M (1 << 5)
5015 : #define IWM_SCAN_CONFIG_RATE_48M (1 << 6)
5016 : #define IWM_SCAN_CONFIG_RATE_54M (1 << 7)
5017 : /* CCK basic rates */
5018 : #define IWM_SCAN_CONFIG_RATE_1M (1 << 8)
5019 : #define IWM_SCAN_CONFIG_RATE_2M (1 << 9)
5020 : #define IWM_SCAN_CONFIG_RATE_5M (1 << 10)
5021 : #define IWM_SCAN_CONFIG_RATE_11M (1 << 11)
5022 :
5023 : /* Bits 16-27 are for supported rates */
5024 : #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16)
5025 :
5026 : #define IWM_CHANNEL_FLAG_EBS (1 << 0)
5027 : #define IWM_CHANNEL_FLAG_ACCURATE_EBS (1 << 1)
5028 : #define IWM_CHANNEL_FLAG_EBS_ADD (1 << 2)
5029 : #define IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE (1 << 3)
5030 :
5031 : /**
5032 : * struct iwm_scan_config
5033 : * @flags: enum scan_config_flags
5034 : * @tx_chains: valid_tx antenna - ANT_* definitions
5035 : * @rx_chains: valid_rx antenna - ANT_* definitions
5036 : * @legacy_rates: default legacy rates - enum scan_config_rates
5037 : * @out_of_channel_time: default max out of serving channel time
5038 : * @suspend_time: default max suspend time
5039 : * @dwell_active: default dwell time for active scan
5040 : * @dwell_passive: default dwell time for passive scan
5041 : * @dwell_fragmented: default dwell time for fragmented scan
5042 : * @dwell_extended: default dwell time for channels 1, 6 and 11
5043 : * @mac_addr: default mac address to be used in probes
5044 : * @bcast_sta_id: the index of the station in the fw
5045 : * @channel_flags: default channel flags - enum iwm_channel_flags
5046 : * scan_config_channel_flag
5047 : * @channel_array: default supported channels
5048 : */
5049 : struct iwm_scan_config {
5050 : uint32_t flags;
5051 : uint32_t tx_chains;
5052 : uint32_t rx_chains;
5053 : uint32_t legacy_rates;
5054 : uint32_t out_of_channel_time;
5055 : uint32_t suspend_time;
5056 : uint8_t dwell_active;
5057 : uint8_t dwell_passive;
5058 : uint8_t dwell_fragmented;
5059 : uint8_t dwell_extended;
5060 : uint8_t mac_addr[ETHER_ADDR_LEN];
5061 : uint8_t bcast_sta_id;
5062 : uint8_t channel_flags;
5063 : uint8_t channel_array[];
5064 : } __packed; /* SCAN_CONFIG_DB_CMD_API_S */
5065 :
5066 : /**
5067 : * iwm_umac_scan_flags
5068 : *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request
5069 : * can be preempted by other scan requests with higher priority.
5070 : * The low priority scan will be resumed when the higher proirity scan is
5071 : * completed.
5072 : *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver
5073 : * when scan starts.
5074 : */
5075 : #define IWM_UMAC_SCAN_FLAG_PREEMPTIVE (1 << 0)
5076 : #define IWM_UMAC_SCAN_FLAG_START_NOTIF (1 << 1)
5077 :
5078 : #define IWM_UMAC_SCAN_UID_TYPE_OFFSET 0
5079 : #define IWM_UMAC_SCAN_UID_SEQ_OFFSET 8
5080 :
5081 : #define IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC (1 << 0)
5082 : #define IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT (1 << 1)
5083 : #define IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL (1 << 2)
5084 : #define IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE (1 << 3)
5085 : #define IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT (1 << 4)
5086 : #define IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE (1 << 5)
5087 : #define IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID (1 << 6)
5088 : #define IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED (1 << 7)
5089 : #define IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED (1 << 8)
5090 : #define IWM_UMAC_SCAN_GEN_FLAGS_MATCH (1 << 9)
5091 : #define IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL (1 << 10)
5092 :
5093 : /**
5094 : * struct iwm_scan_channel_cfg_umac
5095 : * @flags: bitmap - 0-19: directed scan to i'th ssid.
5096 : * @channel_num: channel number 1-13 etc.
5097 : * @iter_count: repetition count for the channel.
5098 : * @iter_interval: interval between two scan iterations on one channel.
5099 : */
5100 : struct iwm_scan_channel_cfg_umac {
5101 : uint32_t flags;
5102 : uint8_t channel_num;
5103 : uint8_t iter_count;
5104 : uint16_t iter_interval;
5105 : } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */
5106 :
5107 : /**
5108 : * struct iwm_scan_umac_schedule
5109 : * @interval: interval in seconds between scan iterations
5110 : * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop
5111 : * @reserved: for alignment and future use
5112 : */
5113 : struct iwm_scan_umac_schedule {
5114 : uint16_t interval;
5115 : uint8_t iter_count;
5116 : uint8_t reserved;
5117 : } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */
5118 :
5119 : /**
5120 : * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command
5121 : * parameters following channels configuration array.
5122 : * @schedule: two scheduling plans.
5123 : * @delay: delay in TUs before starting the first scan iteration
5124 : * @reserved: for future use and alignment
5125 : * @preq: probe request with IEs blocks
5126 : * @direct_scan: list of SSIDs for directed active scan
5127 : */
5128 : struct iwm_scan_req_umac_tail {
5129 : /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */
5130 : struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS];
5131 : uint16_t delay;
5132 : uint16_t reserved;
5133 : /* SCAN_PROBE_PARAMS_API_S_VER_1 */
5134 : struct iwm_scan_probe_req preq;
5135 : struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
5136 : } __packed;
5137 :
5138 : /**
5139 : * struct iwm_scan_req_umac
5140 : * @flags: &enum iwm_umac_scan_flags
5141 : * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5142 : * @ooc_priority: out of channel priority - &enum iwm_scan_priority
5143 : * @general_flags: &enum iwm_umac_scan_general_flags
5144 : * @extended_dwell: dwell time for channels 1, 6 and 11
5145 : * @active_dwell: dwell time for active scan
5146 : * @passive_dwell: dwell time for passive scan
5147 : * @fragmented_dwell: dwell time for fragmented passive scan
5148 : * @max_out_time: max out of serving channel time
5149 : * @suspend_time: max suspend time
5150 : * @scan_priority: scan internal prioritization &enum iwm_scan_priority
5151 : * @channel_flags: &enum iwm_scan_channel_flags
5152 : * @n_channels: num of channels in scan request
5153 : * @reserved: for future use and alignment
5154 : * @data: &struct iwm_scan_channel_cfg_umac and
5155 : * &struct iwm_scan_req_umac_tail
5156 : */
5157 : struct iwm_scan_req_umac {
5158 : uint32_t flags;
5159 : uint32_t uid;
5160 : uint32_t ooc_priority;
5161 : /* SCAN_GENERAL_PARAMS_API_S_VER_1 */
5162 : uint32_t general_flags;
5163 : uint8_t extended_dwell;
5164 : uint8_t active_dwell;
5165 : uint8_t passive_dwell;
5166 : uint8_t fragmented_dwell;
5167 : uint32_t max_out_time;
5168 : uint32_t suspend_time;
5169 : uint32_t scan_priority;
5170 : /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */
5171 : uint8_t channel_flags;
5172 : uint8_t n_channels;
5173 : uint16_t reserved;
5174 : uint8_t data[];
5175 : } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */
5176 :
5177 : /**
5178 : * struct iwm_umac_scan_abort
5179 : * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5180 : * @flags: reserved
5181 : */
5182 : struct iwm_umac_scan_abort {
5183 : uint32_t uid;
5184 : uint32_t flags;
5185 : } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */
5186 :
5187 : /**
5188 : * struct iwm_umac_scan_complete
5189 : * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5190 : * @last_schedule: last scheduling line
5191 : * @last_iter: last scan iteration number
5192 : * @scan status: &enum iwm_scan_offload_complete_status
5193 : * @ebs_status: &enum iwm_scan_ebs_status
5194 : * @time_from_last_iter: time elapsed from last iteration
5195 : * @reserved: for future use
5196 : */
5197 : struct iwm_umac_scan_complete {
5198 : uint32_t uid;
5199 : uint8_t last_schedule;
5200 : uint8_t last_iter;
5201 : uint8_t status;
5202 : uint8_t ebs_status;
5203 : uint32_t time_from_last_iter;
5204 : uint32_t reserved;
5205 : } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */
5206 :
5207 : #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5
5208 : /**
5209 : * struct iwm_scan_offload_profile_match - match information
5210 : * @bssid: matched bssid
5211 : * @channel: channel where the match occurred
5212 : * @energy:
5213 : * @matching_feature:
5214 : * @matching_channels: bitmap of channels that matched, referencing
5215 : * the channels passed in tue scan offload request
5216 : */
5217 : struct iwm_scan_offload_profile_match {
5218 : uint8_t bssid[ETHER_ADDR_LEN];
5219 : uint16_t reserved;
5220 : uint8_t channel;
5221 : uint8_t energy;
5222 : uint8_t matching_feature;
5223 : uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN];
5224 : } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */
5225 :
5226 : /**
5227 : * struct iwm_scan_offload_profiles_query - match results query response
5228 : * @matched_profiles: bitmap of matched profiles, referencing the
5229 : * matches passed in the scan offload request
5230 : * @last_scan_age: age of the last offloaded scan
5231 : * @n_scans_done: number of offloaded scans done
5232 : * @gp2_d0u: GP2 when D0U occurred
5233 : * @gp2_invoked: GP2 when scan offload was invoked
5234 : * @resume_while_scanning: not used
5235 : * @self_recovery: obsolete
5236 : * @reserved: reserved
5237 : * @matches: array of match information, one for each match
5238 : */
5239 : struct iwm_scan_offload_profiles_query {
5240 : uint32_t matched_profiles;
5241 : uint32_t last_scan_age;
5242 : uint32_t n_scans_done;
5243 : uint32_t gp2_d0u;
5244 : uint32_t gp2_invoked;
5245 : uint8_t resume_while_scanning;
5246 : uint8_t self_recovery;
5247 : uint16_t reserved;
5248 : struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES];
5249 : } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */
5250 :
5251 : /**
5252 : * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration
5253 : * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5254 : * @scanned_channels: number of channels scanned and number of valid elements in
5255 : * results array
5256 : * @status: one of SCAN_COMP_STATUS_*
5257 : * @bt_status: BT on/off status
5258 : * @last_channel: last channel that was scanned
5259 : * @tsf_low: TSF timer (lower half) in usecs
5260 : * @tsf_high: TSF timer (higher half) in usecs
5261 : * @results: array of scan results, only "scanned_channels" of them are valid
5262 : */
5263 : struct iwm_umac_scan_iter_complete_notif {
5264 : uint32_t uid;
5265 : uint8_t scanned_channels;
5266 : uint8_t status;
5267 : uint8_t bt_status;
5268 : uint8_t last_channel;
5269 : uint32_t tsf_low;
5270 : uint32_t tsf_high;
5271 : struct iwm_scan_results_notif results[];
5272 : } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */
5273 :
5274 : #define IWM_GSCAN_START_CMD 0x0
5275 : #define IWM_GSCAN_STOP_CMD 0x1
5276 : #define IWM_GSCAN_SET_HOTLIST_CMD 0x2
5277 : #define IWM_GSCAN_RESET_HOTLIST_CMD 0x3
5278 : #define IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD 0x4
5279 : #define IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD 0x5
5280 : #define IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT 0xFD
5281 : #define IWM_GSCAN_HOTLIST_CHANGE_EVENT 0xFE
5282 : #define IWM_GSCAN_RESULTS_AVAILABLE_EVENT 0xFF
5283 :
5284 : /* STA API */
5285 :
5286 : /**
5287 : * flags for the ADD_STA host command
5288 : * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL:
5289 : * @IWM_STA_FLG_REDUCED_TX_PWR_DATA:
5290 : * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled
5291 : * @IWM_STA_FLG_PS: set if STA is in Power Save
5292 : * @IWM_STA_FLG_INVALID: set if STA is invalid
5293 : * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled
5294 : * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs
5295 : * @IWM_STA_FLG_DRAIN_FLOW: drain flow
5296 : * @IWM_STA_FLG_PAN: STA is for PAN interface
5297 : * @IWM_STA_FLG_CLASS_AUTH:
5298 : * @IWM_STA_FLG_CLASS_ASSOC:
5299 : * @IWM_STA_FLG_CLASS_MIMO_PROT:
5300 : * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU
5301 : * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation
5302 : * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is
5303 : * initialised by driver and can be updated by fw upon reception of
5304 : * action frames that can change the channel width. When cleared the fw
5305 : * will send all the frames in 20MHz even when FAT channel is requested.
5306 : * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the
5307 : * driver and can be updated by fw upon reception of action frames.
5308 : * @IWM_STA_FLG_MFP_EN: Management Frame Protection
5309 : */
5310 : #define IWM_STA_FLG_REDUCED_TX_PWR_CTRL (1 << 3)
5311 : #define IWM_STA_FLG_REDUCED_TX_PWR_DATA (1 << 6)
5312 :
5313 : #define IWM_STA_FLG_DISABLE_TX (1 << 4)
5314 :
5315 : #define IWM_STA_FLG_PS (1 << 8)
5316 : #define IWM_STA_FLG_DRAIN_FLOW (1 << 12)
5317 : #define IWM_STA_FLG_PAN (1 << 13)
5318 : #define IWM_STA_FLG_CLASS_AUTH (1 << 14)
5319 : #define IWM_STA_FLG_CLASS_ASSOC (1 << 15)
5320 : #define IWM_STA_FLG_RTS_MIMO_PROT (1 << 17)
5321 :
5322 : #define IWM_STA_FLG_MAX_AGG_SIZE_SHIFT 19
5323 : #define IWM_STA_FLG_MAX_AGG_SIZE_8K (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
5324 : #define IWM_STA_FLG_MAX_AGG_SIZE_16K (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
5325 : #define IWM_STA_FLG_MAX_AGG_SIZE_32K (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
5326 : #define IWM_STA_FLG_MAX_AGG_SIZE_64K (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
5327 : #define IWM_STA_FLG_MAX_AGG_SIZE_128K (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
5328 : #define IWM_STA_FLG_MAX_AGG_SIZE_256K (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
5329 : #define IWM_STA_FLG_MAX_AGG_SIZE_512K (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
5330 : #define IWM_STA_FLG_MAX_AGG_SIZE_1024K (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
5331 : #define IWM_STA_FLG_MAX_AGG_SIZE_MSK (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
5332 :
5333 : #define IWM_STA_FLG_AGG_MPDU_DENS_SHIFT 23
5334 : #define IWM_STA_FLG_AGG_MPDU_DENS_2US (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)
5335 : #define IWM_STA_FLG_AGG_MPDU_DENS_4US (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)
5336 : #define IWM_STA_FLG_AGG_MPDU_DENS_8US (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)
5337 : #define IWM_STA_FLG_AGG_MPDU_DENS_16US (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)
5338 : #define IWM_STA_FLG_AGG_MPDU_DENS_MSK (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)
5339 :
5340 : #define IWM_STA_FLG_FAT_EN_20MHZ (0 << 26)
5341 : #define IWM_STA_FLG_FAT_EN_40MHZ (1 << 26)
5342 : #define IWM_STA_FLG_FAT_EN_80MHZ (2 << 26)
5343 : #define IWM_STA_FLG_FAT_EN_160MHZ (3 << 26)
5344 : #define IWM_STA_FLG_FAT_EN_MSK (3 << 26)
5345 :
5346 : #define IWM_STA_FLG_MIMO_EN_SISO (0 << 28)
5347 : #define IWM_STA_FLG_MIMO_EN_MIMO2 (1 << 28)
5348 : #define IWM_STA_FLG_MIMO_EN_MIMO3 (2 << 28)
5349 : #define IWM_STA_FLG_MIMO_EN_MSK (3 << 28)
5350 :
5351 : /**
5352 : * key flags for the ADD_STA host command
5353 : * @IWM_STA_KEY_FLG_NO_ENC: no encryption
5354 : * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm
5355 : * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm
5356 : * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm
5357 : * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support)
5358 : * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm
5359 : * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm
5360 : * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value
5361 : * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from
5362 : * station info array (1 - n 1X mode)
5363 : * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key
5364 : * @IWM_STA_KEY_NOT_VALID: key is invalid
5365 : * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key
5366 : * @IWM_STA_KEY_MULTICAST: set for multical key
5367 : * @IWM_STA_KEY_MFP: key is used for Management Frame Protection
5368 : */
5369 : #define IWM_STA_KEY_FLG_NO_ENC (0 << 0)
5370 : #define IWM_STA_KEY_FLG_WEP (1 << 0)
5371 : #define IWM_STA_KEY_FLG_CCM (2 << 0)
5372 : #define IWM_STA_KEY_FLG_TKIP (3 << 0)
5373 : #define IWM_STA_KEY_FLG_EXT (4 << 0)
5374 : #define IWM_STA_KEY_FLG_CMAC (6 << 0)
5375 : #define IWM_STA_KEY_FLG_ENC_UNKNOWN (7 << 0)
5376 : #define IWM_STA_KEY_FLG_EN_MSK (7 << 0)
5377 : #define IWM_STA_KEY_FLG_WEP_KEY_MAP (1 << 3)
5378 : #define IWM_STA_KEY_FLG_KEYID_POS 8
5379 : #define IWM_STA_KEY_FLG_KEYID_MSK (3 << IWM_STA_KEY_FLG_KEYID_POS)
5380 : #define IWM_STA_KEY_NOT_VALID (1 << 11)
5381 : #define IWM_STA_KEY_FLG_WEP_13BYTES (1 << 12)
5382 : #define IWM_STA_KEY_MULTICAST (1 << 14)
5383 : #define IWM_STA_KEY_MFP (1 << 15)
5384 :
5385 : /**
5386 : * indicate to the fw what flag are being changed
5387 : * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue
5388 : * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx
5389 : * @IWM_STA_MODIFY_TX_RATE: unused
5390 : * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid
5391 : * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid
5392 : * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count
5393 : * @IWM_STA_MODIFY_PROT_TH:
5394 : * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station
5395 : */
5396 : #define IWM_STA_MODIFY_QUEUE_REMOVAL (1 << 0)
5397 : #define IWM_STA_MODIFY_TID_DISABLE_TX (1 << 1)
5398 : #define IWM_STA_MODIFY_TX_RATE (1 << 2)
5399 : #define IWM_STA_MODIFY_ADD_BA_TID (1 << 3)
5400 : #define IWM_STA_MODIFY_REMOVE_BA_TID (1 << 4)
5401 : #define IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT (1 << 5)
5402 : #define IWM_STA_MODIFY_PROT_TH (1 << 6)
5403 : #define IWM_STA_MODIFY_QUEUES (1 << 7)
5404 :
5405 : #define IWM_STA_MODE_MODIFY 1
5406 :
5407 : /**
5408 : * type of sleep of the station
5409 : * @IWM_STA_SLEEP_STATE_AWAKE:
5410 : * @IWM_STA_SLEEP_STATE_PS_POLL:
5411 : * @IWM_STA_SLEEP_STATE_UAPSD:
5412 : * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on
5413 : * (last) released frame
5414 : */
5415 : #define IWM_STA_SLEEP_STATE_AWAKE 0
5416 : #define IWM_STA_SLEEP_STATE_PS_POLL (1 << 0)
5417 : #define IWM_STA_SLEEP_STATE_UAPSD (1 << 1)
5418 : #define IWM_STA_SLEEP_STATE_MOREDATA (1 << 2)
5419 :
5420 : /* STA ID and color bits definitions */
5421 : #define IWM_STA_ID_SEED (0x0f)
5422 : #define IWM_STA_ID_POS (0)
5423 : #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS)
5424 :
5425 : #define IWM_STA_COLOR_SEED (0x7)
5426 : #define IWM_STA_COLOR_POS (4)
5427 : #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS)
5428 :
5429 : #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \
5430 : (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS)
5431 : #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \
5432 : (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS)
5433 :
5434 : #define IWM_STA_KEY_MAX_NUM (16)
5435 : #define IWM_STA_KEY_IDX_INVALID (0xff)
5436 : #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4)
5437 : #define IWM_MAX_GLOBAL_KEYS (4)
5438 : #define IWM_STA_KEY_LEN_WEP40 (5)
5439 : #define IWM_STA_KEY_LEN_WEP104 (13)
5440 :
5441 : /**
5442 : * struct iwm_keyinfo - key information
5443 : * @key_flags: type %iwm_sta_key_flag
5444 : * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5445 : * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5446 : * @key_offset: key offset in the fw's key table
5447 : * @key: 16-byte unicast decryption key
5448 : * @tx_secur_seq_cnt: initial RSC / PN needed for replay check
5449 : * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only
5450 : * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only
5451 : */
5452 : struct iwm_keyinfo {
5453 : uint16_t key_flags;
5454 : uint8_t tkip_rx_tsc_byte2;
5455 : uint8_t reserved1;
5456 : uint16_t tkip_rx_ttak[5];
5457 : uint8_t key_offset;
5458 : uint8_t reserved2;
5459 : uint8_t key[16];
5460 : uint64_t tx_secur_seq_cnt;
5461 : uint64_t hw_tkip_mic_rx_key;
5462 : uint64_t hw_tkip_mic_tx_key;
5463 : } __packed;
5464 :
5465 : #define IWM_ADD_STA_STATUS_MASK 0xFF
5466 : #define IWM_ADD_STA_BAID_VALID_MASK 0x8000
5467 : #define IWM_ADD_STA_BAID_MASK 0x7F00
5468 : #define IWM_ADD_STA_BAID_SHIFT 8
5469 :
5470 : /**
5471 : * struct iwm_add_sta_cmd_v7 - Add/modify a station in the fw's sta table.
5472 : * ( REPLY_ADD_STA = 0x18 )
5473 : * @add_modify: 1: modify existing, 0: add new station
5474 : * @awake_acs:
5475 : * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
5476 : * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field.
5477 : * @mac_id_n_color: the Mac context this station belongs to
5478 : * @addr[ETHER_ADDR_LEN]: station's MAC address
5479 : * @sta_id: index of station in uCode's station table
5480 : * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave
5481 : * alone. 1 - modify, 0 - don't change.
5482 : * @station_flags: look at %iwm_sta_flags
5483 : * @station_flags_msk: what of %station_flags have changed
5484 : * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
5485 : * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set
5486 : * add_immediate_ba_ssn.
5487 : * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
5488 : * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field
5489 : * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
5490 : * add_immediate_ba_tid.
5491 : * @sleep_tx_count: number of packets to transmit to station even though it is
5492 : * asleep. Used to synchronise PS-poll and u-APSD responses while ucode
5493 : * keeps track of STA sleep state.
5494 : * @sleep_state_flags: Look at %iwm_sta_sleep_flag.
5495 : * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP
5496 : * mac-addr.
5497 : * @beamform_flags: beam forming controls
5498 : * @tfd_queue_msk: tfd queues used by this station
5499 : *
5500 : * The device contains an internal table of per-station information, with info
5501 : * on security keys, aggregation parameters, and Tx rates for initial Tx
5502 : * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD).
5503 : *
5504 : * ADD_STA sets up the table entry for one station, either creating a new
5505 : * entry, or modifying a pre-existing one.
5506 : */
5507 : struct iwm_add_sta_cmd_v7 {
5508 : uint8_t add_modify;
5509 : uint8_t awake_acs;
5510 : uint16_t tid_disable_tx;
5511 : uint32_t mac_id_n_color;
5512 : uint8_t addr[ETHER_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */
5513 : uint16_t reserved2;
5514 : uint8_t sta_id;
5515 : uint8_t modify_mask;
5516 : uint16_t reserved3;
5517 : uint32_t station_flags;
5518 : uint32_t station_flags_msk;
5519 : uint8_t add_immediate_ba_tid;
5520 : uint8_t remove_immediate_ba_tid;
5521 : uint16_t add_immediate_ba_ssn;
5522 : uint16_t sleep_tx_count;
5523 : uint16_t sleep_state_flags;
5524 : uint16_t assoc_id;
5525 : uint16_t beamform_flags;
5526 : uint32_t tfd_queue_msk;
5527 : } __packed; /* ADD_STA_CMD_API_S_VER_7 */
5528 :
5529 : /**
5530 : * struct iwm_add_sta_key_cmd - add/modify sta key
5531 : * ( IWM_REPLY_ADD_STA_KEY = 0x17 )
5532 : * @sta_id: index of station in uCode's station table
5533 : * @key_offset: key offset in key storage
5534 : * @key_flags: type %iwm_sta_key_flag
5535 : * @key: key material data
5536 : * @key2: key material data
5537 : * @rx_secur_seq_cnt: RX security sequence counter for the key
5538 : * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5539 : * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5540 : */
5541 : struct iwm_add_sta_key_cmd {
5542 : uint8_t sta_id;
5543 : uint8_t key_offset;
5544 : uint16_t key_flags;
5545 : uint8_t key[16];
5546 : uint8_t key2[16];
5547 : uint8_t rx_secur_seq_cnt[16];
5548 : uint8_t tkip_rx_tsc_byte2;
5549 : uint8_t reserved;
5550 : uint16_t tkip_rx_ttak[5];
5551 : } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */
5552 :
5553 : /**
5554 : * status in the response to ADD_STA command
5555 : * @IWM_ADD_STA_SUCCESS: operation was executed successfully
5556 : * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table
5557 : * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session
5558 : * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station
5559 : * that doesn't exist.
5560 : */
5561 : #define IWM_ADD_STA_SUCCESS 0x1
5562 : #define IWM_ADD_STA_STATIONS_OVERLOAD 0x2
5563 : #define IWM_ADD_STA_IMMEDIATE_BA_FAILURE 0x4
5564 : #define IWM_ADD_STA_MODIFY_NON_EXISTING_STA 0x8
5565 :
5566 : /**
5567 : * struct iwm_rm_sta_cmd - Add / modify a station in the fw's station table
5568 : * ( IWM_REMOVE_STA = 0x19 )
5569 : * @sta_id: the station id of the station to be removed
5570 : */
5571 : struct iwm_rm_sta_cmd {
5572 : uint8_t sta_id;
5573 : uint8_t reserved[3];
5574 : } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */
5575 :
5576 : /**
5577 : * struct iwm_mgmt_mcast_key_cmd
5578 : * ( IWM_MGMT_MCAST_KEY = 0x1f )
5579 : * @ctrl_flags: %iwm_sta_key_flag
5580 : * @IGTK:
5581 : * @K1: IGTK master key
5582 : * @K2: IGTK sub key
5583 : * @sta_id: station ID that support IGTK
5584 : * @key_id:
5585 : * @receive_seq_cnt: initial RSC/PN needed for replay check
5586 : */
5587 : struct iwm_mgmt_mcast_key_cmd {
5588 : uint32_t ctrl_flags;
5589 : uint8_t IGTK[16];
5590 : uint8_t K1[16];
5591 : uint8_t K2[16];
5592 : uint32_t key_id;
5593 : uint32_t sta_id;
5594 : uint64_t receive_seq_cnt;
5595 : } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */
5596 :
5597 : struct iwm_wep_key {
5598 : uint8_t key_index;
5599 : uint8_t key_offset;
5600 : uint16_t reserved1;
5601 : uint8_t key_size;
5602 : uint8_t reserved2[3];
5603 : uint8_t key[16];
5604 : } __packed;
5605 :
5606 : struct iwm_wep_key_cmd {
5607 : uint32_t mac_id_n_color;
5608 : uint8_t num_keys;
5609 : uint8_t decryption_type;
5610 : uint8_t flags;
5611 : uint8_t reserved;
5612 : struct iwm_wep_key wep_key[0];
5613 : } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */
5614 :
5615 : /*
5616 : * BT coex
5617 : */
5618 :
5619 : #define IWM_BT_COEX_DISABLE 0x0
5620 : #define IWM_BT_COEX_NW 0x1
5621 : #define IWM_BT_COEX_BT 0x2
5622 : #define IWM_BT_COEX_WIFI 0x3
5623 : /* BT_COEX_MODES_E */
5624 :
5625 : #define IWM_BT_COEX_MPLUT_ENABLED (1 << 0)
5626 : #define IWM_BT_COEX_MPLUT_BOOST_ENABLED (1 << 1)
5627 : #define IWM_BT_COEX_SYNC2SCO_ENABLED (1 << 2)
5628 : #define IWM_BT_COEX_CORUN_ENABLED (1 << 3)
5629 : #define IWM_BT_COEX_HIGH_BAND_RET (1 << 4)
5630 : /* BT_COEX_MODULES_ENABLE_E_VER_1 */
5631 :
5632 : /**
5633 : * struct iwm_bt_coex_cmd - bt coex configuration command
5634 : * @mode: enum %iwm_bt_coex_mode
5635 : * @enabled_modules: enum %iwm_bt_coex_enabled_modules
5636 : *
5637 : * The structure is used for the BT_COEX command.
5638 : */
5639 : struct iwm_bt_coex_cmd {
5640 : uint32_t mode;
5641 : uint32_t enabled_modules;
5642 : } __packed; /* BT_COEX_CMD_API_S_VER_6 */
5643 :
5644 :
5645 : /*
5646 : * Location Aware Regulatory (LAR) API - MCC updates
5647 : */
5648 :
5649 : /**
5650 : * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic
5651 : * regulatory profile according to the given MCC (Mobile Country Code).
5652 : * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
5653 : * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
5654 : * MCC in the cmd response will be the relevant MCC in the NVM.
5655 : * @mcc: given mobile country code
5656 : * @source_id: the source from where we got the MCC, see iwm_mcc_source
5657 : * @reserved: reserved for alignment
5658 : */
5659 : struct iwm_mcc_update_cmd_v1 {
5660 : uint16_t mcc;
5661 : uint8_t source_id;
5662 : uint8_t reserved;
5663 : } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */
5664 :
5665 : /**
5666 : * struct iwm_mcc_update_cmd - Request the device to update geographic
5667 : * regulatory profile according to the given MCC (Mobile Country Code).
5668 : * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
5669 : * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
5670 : * MCC in the cmd response will be the relevant MCC in the NVM.
5671 : * @mcc: given mobile country code
5672 : * @source_id: the source from where we got the MCC, see iwm_mcc_source
5673 : * @reserved: reserved for alignment
5674 : * @key: integrity key for MCC API OEM testing
5675 : * @reserved2: reserved
5676 : */
5677 : struct iwm_mcc_update_cmd {
5678 : uint16_t mcc;
5679 : uint8_t source_id;
5680 : uint8_t reserved;
5681 : uint32_t key;
5682 : uint32_t reserved2[5];
5683 : } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */
5684 :
5685 : /**
5686 : * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD.
5687 : * Contains the new channel control profile map, if changed, and the new MCC
5688 : * (mobile country code).
5689 : * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
5690 : * @status: see &enum iwm_mcc_update_status
5691 : * @mcc: the new applied MCC
5692 : * @cap: capabilities for all channels which matches the MCC
5693 : * @source_id: the MCC source, see iwm_mcc_source
5694 : * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
5695 : * channels, depending on platform)
5696 : * @channels: channel control data map, DWORD for each channel. Only the first
5697 : * 16bits are used.
5698 : */
5699 : struct iwm_mcc_update_resp_v1 {
5700 : uint32_t status;
5701 : uint16_t mcc;
5702 : uint8_t cap;
5703 : uint8_t source_id;
5704 : uint32_t n_channels;
5705 : uint32_t channels[0];
5706 : } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */
5707 :
5708 : /**
5709 : * iwm_mcc_update_resp - response to MCC_UPDATE_CMD.
5710 : * Contains the new channel control profile map, if changed, and the new MCC
5711 : * (mobile country code).
5712 : * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
5713 : * @status: see &enum iwm_mcc_update_status
5714 : * @mcc: the new applied MCC
5715 : * @cap: capabilities for all channels which matches the MCC
5716 : * @source_id: the MCC source, see iwm_mcc_source
5717 : * @time: time elapsed from the MCC test start (in 30 seconds TU)
5718 : * @reserved: reserved.
5719 : * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
5720 : * channels, depending on platform)
5721 : * @channels: channel control data map, DWORD for each channel. Only the first
5722 : * 16bits are used.
5723 : */
5724 : struct iwm_mcc_update_resp {
5725 : uint32_t status;
5726 : uint16_t mcc;
5727 : uint8_t cap;
5728 : uint8_t source_id;
5729 : uint16_t time;
5730 : uint16_t reserved;
5731 : uint32_t n_channels;
5732 : uint32_t channels[0];
5733 : } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */
5734 :
5735 : /**
5736 : * struct iwm_mcc_chub_notif - chub notifies of mcc change
5737 : * (MCC_CHUB_UPDATE_CMD = 0xc9)
5738 : * The Chub (Communication Hub, CommsHUB) is a HW component that connects to
5739 : * the cellular and connectivity cores that gets updates of the mcc, and
5740 : * notifies the ucode directly of any mcc change.
5741 : * The ucode requests the driver to request the device to update geographic
5742 : * regulatory profile according to the given MCC (Mobile Country Code).
5743 : * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
5744 : * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
5745 : * MCC in the cmd response will be the relevant MCC in the NVM.
5746 : * @mcc: given mobile country code
5747 : * @source_id: identity of the change originator, see iwm_mcc_source
5748 : * @reserved1: reserved for alignment
5749 : */
5750 : struct iwm_mcc_chub_notif {
5751 : uint16_t mcc;
5752 : uint8_t source_id;
5753 : uint8_t reserved1;
5754 : } __packed; /* LAR_MCC_NOTIFY_S */
5755 :
5756 : #define IWM_MCC_RESP_NEW_CHAN_PROFILE 0
5757 : #define IWM_MCC_RESP_SAME_CHAN_PROFILE 1
5758 : #define IWM_MCC_RESP_INVALID 2
5759 : #define IWM_MCC_RESP_NVM_DISABLED 3
5760 : #define IWM_MCC_RESP_ILLEGAL 4
5761 : #define IWM_MCC_RESP_LOW_PRIORITY 5
5762 : #define IWM_MCC_RESP_TEST_MODE_ACTIVE 6
5763 : #define IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE 7
5764 : #define IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE 8
5765 :
5766 : #define IWM_MCC_SOURCE_OLD_FW 0
5767 : #define IWM_MCC_SOURCE_ME 1
5768 : #define IWM_MCC_SOURCE_BIOS 2
5769 : #define IWM_MCC_SOURCE_3G_LTE_HOST 3
5770 : #define IWM_MCC_SOURCE_3G_LTE_DEVICE 4
5771 : #define IWM_MCC_SOURCE_WIFI 5
5772 : #define IWM_MCC_SOURCE_RESERVED 6
5773 : #define IWM_MCC_SOURCE_DEFAULT 7
5774 : #define IWM_MCC_SOURCE_UNINITIALIZED 8
5775 : #define IWM_MCC_SOURCE_MCC_API 9
5776 : #define IWM_MCC_SOURCE_GET_CURRENT 0x10
5777 : #define IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE 0x11
5778 :
5779 : /*
5780 : * Some cherry-picked definitions
5781 : */
5782 :
5783 : #define IWM_FRAME_LIMIT 64
5784 :
5785 : /*
5786 : * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811:
5787 : * As the firmware is slowly running out of command IDs and grouping of
5788 : * commands is desirable anyway, the firmware is extending the command
5789 : * header from 4 bytes to 8 bytes to introduce a group (in place of the
5790 : * former flags field, since that's always 0 on commands and thus can
5791 : * be easily used to distinguish between the two).
5792 : *
5793 : * These functions retrieve specific information from the id field in
5794 : * the iwm_host_cmd struct which contains the command id, the group id,
5795 : * and the version of the command.
5796 : */
5797 : static inline uint8_t
5798 0 : iwm_cmd_opcode(uint32_t cmdid)
5799 : {
5800 0 : return cmdid & 0xff;
5801 : }
5802 :
5803 : static inline uint8_t
5804 0 : iwm_cmd_groupid(uint32_t cmdid)
5805 : {
5806 0 : return ((cmdid & 0Xff00) >> 8);
5807 : }
5808 :
5809 : static inline uint8_t
5810 0 : iwm_cmd_version(uint32_t cmdid)
5811 : {
5812 0 : return ((cmdid & 0xff0000) >> 16);
5813 : }
5814 :
5815 : static inline uint32_t
5816 0 : iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version)
5817 : {
5818 0 : return opcode + (groupid << 8) + (version << 16);
5819 : }
5820 :
5821 : /* make uint16_t wide id out of uint8_t group and opcode */
5822 : #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode)
5823 :
5824 : /* due to the conversion, this group is special */
5825 : #define IWM_ALWAYS_LONG_GROUP 1
5826 : #define IWM_SYSTEM_GROUP 4
5827 :
5828 : struct iwm_cmd_header {
5829 : uint8_t code;
5830 : uint8_t flags;
5831 : uint8_t idx;
5832 : uint8_t qid;
5833 : } __packed;
5834 :
5835 : struct iwm_cmd_header_wide {
5836 : uint8_t opcode;
5837 : uint8_t group_id;
5838 : uint8_t idx;
5839 : uint8_t qid;
5840 : uint16_t length;
5841 : uint8_t reserved;
5842 : uint8_t version;
5843 : } __packed;
5844 :
5845 : #define IWM_POWER_SCHEME_CAM 1
5846 : #define IWM_POWER_SCHEME_BPS 2
5847 : #define IWM_POWER_SCHEME_LP 3
5848 :
5849 : #define IWM_DEF_CMD_PAYLOAD_SIZE 320
5850 : #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header))
5851 : #define IWM_CMD_FAILED_MSK 0x40
5852 :
5853 : /**
5854 : * struct iwm_device_cmd
5855 : *
5856 : * For allocation of the command and tx queues, this establishes the overall
5857 : * size of the largest command we send to uCode, except for commands that
5858 : * aren't fully copied and use other TFD space.
5859 : */
5860 : struct iwm_device_cmd {
5861 : union {
5862 : struct {
5863 : struct iwm_cmd_header hdr;
5864 : uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE];
5865 : };
5866 : struct {
5867 : struct iwm_cmd_header_wide hdr_wide;
5868 : uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE -
5869 : sizeof(struct iwm_cmd_header_wide) +
5870 : sizeof(struct iwm_cmd_header)];
5871 : };
5872 : };
5873 : } __packed;
5874 :
5875 : struct iwm_rx_packet {
5876 : /*
5877 : * The first 4 bytes of the RX frame header contain both the RX frame
5878 : * size and some flags.
5879 : * Bit fields:
5880 : * 31: flag flush RB request
5881 : * 30: flag ignore TC (terminal counter) request
5882 : * 29: flag fast IRQ request
5883 : * 28-26: Reserved
5884 : * 25: Offload enabled
5885 : * 24: RPF enabled
5886 : * 23: RSS enabled
5887 : * 22: Checksum enabled
5888 : * 21-16: RX queue
5889 : * 15-14: Reserved
5890 : * 13-00: RX frame size
5891 : */
5892 : uint32_t len_n_flags;
5893 : struct iwm_cmd_header hdr;
5894 : uint8_t data[];
5895 : } __packed;
5896 :
5897 : #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff
5898 : #define IWM_FH_RSCSR_FRAME_INVALID 0x55550000
5899 : #define IWM_FH_RSCSR_FRAME_ALIGN 0x40
5900 : #define IWM_FH_RSCSR_RPA_EN (1 << 25)
5901 : #define IWM_FH_RSCSR_RXQ_POS 16
5902 : #define IWM_FH_RSCSR_RXQ_MASK 0x3F0000
5903 :
5904 : static uint32_t
5905 0 : iwm_rx_packet_len(const struct iwm_rx_packet *pkt)
5906 : {
5907 :
5908 0 : return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK;
5909 : }
5910 :
5911 : static uint32_t
5912 0 : iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt)
5913 : {
5914 :
5915 0 : return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr);
5916 : }
5917 :
5918 :
5919 : #define IWM_MIN_DBM -100
5920 : #define IWM_MAX_DBM -33 /* realistic guess */
5921 :
5922 : #define IWM_READ(sc, reg) \
5923 : bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
5924 :
5925 : #define IWM_WRITE(sc, reg, val) \
5926 : bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
5927 :
5928 : #define IWM_WRITE_1(sc, reg, val) \
5929 : bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
5930 :
5931 : #define IWM_SETBITS(sc, reg, mask) \
5932 : IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask))
5933 :
5934 : #define IWM_CLRBITS(sc, reg, mask) \
5935 : IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))
5936 :
5937 : #define IWM_BARRIER_WRITE(sc) \
5938 : bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
5939 : BUS_SPACE_BARRIER_WRITE)
5940 :
5941 : #define IWM_BARRIER_READ_WRITE(sc) \
5942 : bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
5943 : BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
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